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05/09/2024 07:14:13 AM
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Kbuild
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agp.h
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asm-offsets.h
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asmregs.h
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assembly.h
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atomic.h
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barrier.h
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bitops.h
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bug.h
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bugs.h
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cache.h
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cacheflush.h
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checksum.h
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cmpxchg.h
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compat.h
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compat_ucontext.h
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delay.h
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dma-mapping.h
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dma.h
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dwarf.h
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eisa_bus.h
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eisa_eeprom.h
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elf.h
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fb.h
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fixmap.h
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floppy.h
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ftrace.h
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futex.h
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grfioctl.h
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hardirq.h
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hardware.h
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hash.h
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hugetlb.h
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ide.h
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io.h
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irq.h
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irqflags.h
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kbdleds.h
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kmap_types.h
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ldcw.h
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led.h
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linkage.h
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machdep.h
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mckinley.h
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mmu.h
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mmu_context.h
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mmzone.h
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module.h
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page.h
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parisc-device.h
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parport.h
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pci.h
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pdc.h
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pdc_chassis.h
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pdcpat.h
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perf.h
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perf_event.h
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pgalloc.h
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pgtable.h
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prefetch.h
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processor.h
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psw.h
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ptrace.h
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ropes.h
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rt_sigframe.h
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runway.h
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sections.h
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serial.h
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shmparam.h
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signal.h
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smp.h
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socket.h
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special_insns.h
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spinlock.h
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spinlock_types.h
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string.h
247 bytes
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superio.h
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switch_to.h
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syscall.h
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termios.h
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thread_info.h
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timex.h
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tlb.h
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tlbflush.h
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topology.h
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traps.h
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uaccess.h
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ucontext.h
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unaligned.h
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unistd.h
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unwind.h
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Editing: tlbflush.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _PARISC_TLBFLUSH_H #define _PARISC_TLBFLUSH_H /* TLB flushing routines.... */ #include <linux/mm.h> #include <linux/sched.h> #include <asm/mmu_context.h> /* This is for the serialisation of PxTLB broadcasts. At least on the * N class systems, only one PxTLB inter processor broadcast can be * active at any one time on the Merced bus. This tlb purge * synchronisation is fairly lightweight and harmless so we activate * it on all systems not just the N class. * It is also used to ensure PTE updates are atomic and consistent * with the TLB. */ extern spinlock_t pa_tlb_lock; #define purge_tlb_start(flags) spin_lock_irqsave(&pa_tlb_lock, flags) #define purge_tlb_end(flags) spin_unlock_irqrestore(&pa_tlb_lock, flags) extern void flush_tlb_all(void); extern void flush_tlb_all_local(void *); #define smp_flush_tlb_all() flush_tlb_all() int __flush_tlb_range(unsigned long sid, unsigned long start, unsigned long end); #define flush_tlb_range(vma, start, end) \ __flush_tlb_range((vma)->vm_mm->context, start, end) #define flush_tlb_kernel_range(start, end) \ __flush_tlb_range(0, start, end) /* * flush_tlb_mm() * * The code to switch to a new context is NOT valid for processes * which play with the space id's. Thus, we have to preserve the * space and just flush the entire tlb. However, the compilers, * dynamic linker, etc, do not manipulate space id's, so there * could be a significant performance benefit in switching contexts * and not flushing the whole tlb. */ static inline void flush_tlb_mm(struct mm_struct *mm) { BUG_ON(mm == &init_mm); /* Should never happen */ #if 1 || defined(CONFIG_SMP) /* Except for very small threads, flushing the whole TLB is * faster than using __flush_tlb_range. The pdtlb and pitlb * instructions are very slow because of the TLB broadcast. * It might be faster to do local range flushes on all CPUs * on PA 2.0 systems. */ flush_tlb_all(); #else /* FIXME: currently broken, causing space id and protection ids * to go out of sync, resulting in faults on userspace accesses. * This approach needs further investigation since running many * small applications (e.g., GCC testsuite) is faster on HP-UX. */ if (mm) { if (mm->context != 0) free_sid(mm->context); mm->context = alloc_sid(); if (mm == current->active_mm) load_context(mm->context); } #endif } static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) { unsigned long flags, sid; sid = vma->vm_mm->context; purge_tlb_start(flags); mtsp(sid, 1); pdtlb(addr); if (unlikely(split_tlb)) pitlb(addr); purge_tlb_end(flags); } #endif