OXIESEC PANEL
- Current Dir:
/
/
usr
/
src
/
linux-headers-4.15.0-213
/
arch
/
blackfin
/
include
/
asm
Server IP: 139.59.38.164
Upload:
Create Dir:
Name
Size
Modified
Perms
📁
..
-
05/09/2024 07:14:12 AM
rwxr-xr-x
📄
Kbuild
658 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
atomic.h
1.55 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
barrier.h
2.55 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin-global.h
2.8 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin-lq035q1.h
868 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin5xx_spi.h
2.07 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_can.h
36.04 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_dma.h
5.46 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_pfmon.h
1.11 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_ppi.h
9.01 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_sdh.h
7.2 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_serial.h
17.02 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_simple_timer.h
949 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_sport.h
1.21 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_sport3.h
5.47 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_twi.h
6.25 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfin_watchdog.h
696 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bfrom.h
3.36 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bitops.h
3.45 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
blackfin.h
1.55 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bug.h
1.49 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cache.h
1.47 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cacheflush.h
3.79 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cdef_LPBlackfin.h
18.93 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
checksum.h
899 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
clkdev.h
318 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
clocks.h
1.66 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cmpxchg.h
3.2 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
context.S
5.92 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cplb.h
4.86 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cplbinit.h
1.6 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cpu.h
443 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
def_LPBlackfin.h
28.6 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
delay.h
917 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
dma-mapping.h
1.09 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
dma.h
9.28 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
dpmc.h
18.24 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
early_printk.h
1.09 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
elf.h
4.88 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
entry.h
5.27 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
exec.h
37 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
fixed_code.h
806 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
flat.h
1.41 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ftrace.h
1.37 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
gpio.h
5.91 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
gptimers.h
8.95 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hardirq.h
301 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
io.h
1.52 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ipipe.h
5.81 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ipipe_base.h
2.38 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
irq.h
879 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
irq_handler.h
1.93 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
irqflags.h
7.13 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
kgdb.h
3.23 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
l1layout.h
879 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
linkage.h
205 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
mem_init.h
13.1 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mem_map.h
1.73 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mmu.h
713 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
mmu_context.h
5.35 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
module.h
410 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
nand.h
895 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
nmi.h
195 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
page.h
546 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
page_offset.h
192 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
pci.h
310 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
pda.h
1.86 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
perf_event.h
23 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgtable.h
3 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pm.h
590 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
portmux.h
16.38 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
processor.h
3.21 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pseudo_instructions.h
391 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
ptrace.h
1.19 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
reboot.h
446 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
rwlock.h
142 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
scb.h
445 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
sections.h
2 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
segment.h
226 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
smp.h
1.34 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
spinlock.h
1.87 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
spinlock_types.h
495 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
string.h
1.04 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
switch_to.h
997 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
syscall.h
2.15 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
thread_info.h
2.66 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
time.h
1.33 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
timex.h
477 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
tlb.h
481 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
tlbflush.h
88 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
trace.h
2.67 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
traps.h
4.87 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
uaccess.h
5.79 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
unistd.h
523 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
vga.h
29 bytes
01/28/2018 09:20:33 PM
rw-r--r--
Editing: time.h
Close
/* * asm-blackfin/time.h: * * Copyright 2004-2008 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ #ifndef _ASM_BLACKFIN_TIME_H #define _ASM_BLACKFIN_TIME_H /* * The way that the Blackfin core timer works is: * - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE) * - Every time TSCALE ticks, a 32bit is counted down (TCOUNT) * * If you take the fastest clock (1ns, or 1GHz to make the math work easier) * 10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter * (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need * to use TSCALE, and program it to zero (which is pass CCLK through). * If you feel like using it, try to keep HZ * TIMESCALE to some * value that divides easy (like power of 2). */ #ifndef CONFIG_CPU_FREQ # define TIME_SCALE 1 #else /* * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 . * Whenever we change the Core Clock frequency changes we immediately * adjust the Core Timer Presale Register. This way we don't lose time. */ #define TIME_SCALE 4 # ifdef CONFIG_CYCLES_CLOCKSOURCE extern unsigned long long __bfin_cycles_off; extern unsigned int __bfin_cycles_mod; # endif #endif #if defined(CONFIG_TICKSOURCE_CORETMR) extern void bfin_coretmr_init(void); extern void bfin_coretmr_clockevent_init(void); #endif #endif