OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:12 AM	rwxr-xr-x
📄 Kbuild	658 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	2.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin-global.h	2.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin-lq035q1.h	868 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin5xx_spi.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_can.h	36.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_dma.h	5.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_pfmon.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_ppi.h	9.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_sdh.h	7.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_serial.h	17.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_simple_timer.h	949 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_sport.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_sport3.h	5.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_twi.h	6.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_watchdog.h	696 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfrom.h	3.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 blackfin.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	1.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	3.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cdef_LPBlackfin.h	18.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	899 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clkdev.h	318 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocks.h	1.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 context.S	5.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cplb.h	4.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cplbinit.h	1.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu.h	443 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 def_LPBlackfin.h	28.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	917 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	9.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dpmc.h	18.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 early_printk.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	4.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry.h	5.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	37 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixed_code.h	806 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gpio.h	5.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gptimers.h	8.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	301 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	1.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipipe.h	5.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipipe_base.h	2.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	879 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_handler.h	1.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	7.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	3.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 l1layout.h	879 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	205 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mem_init.h	13.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mem_map.h	1.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	713 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	5.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	410 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nand.h	895 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nmi.h	195 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	546 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_offset.h	192 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	310 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pda.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	23 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm.h	590 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 portmux.h	16.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	3.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pseudo_instructions.h	391 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reboot.h	446 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rwlock.h	142 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 scb.h	445 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 segment.h	226 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	1.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	495 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	997 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 time.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	477 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	481 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	88 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 trace.h	2.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	4.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	5.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	523 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	29 bytes	01/28/2018 09:20:33 PM	rw-r--r--

Editing: bfin_sdh.h

/*
 * Blackfin Secure Digital Host (SDH) definitions
 *
 * Copyright 2008-2010 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef __BFIN_SDH_H__
#define __BFIN_SDH_H__

/* Platform resources */
struct bfin_sd_host {
	int dma_chan;
	int irq_int0;
	int irq_int1;
	u16 pin_req[7];
};

/* SDH_COMMAND bitmasks */
#define CMD_IDX            0x3f        /* Command Index */
#define CMD_RSP            (1 << 6)    /* Response */
#define CMD_L_RSP          (1 << 7)    /* Long Response */
#define CMD_INT_E          (1 << 8)    /* Command Interrupt */
#define CMD_PEND_E         (1 << 9)    /* Command Pending */
#define CMD_E              (1 << 10)   /* Command Enable */
#ifdef RSI_BLKSZ
#define CMD_CRC_CHECK_D    (1 << 11)   /* CRC Check is disabled */
#define CMD_DATA0_BUSY     (1 << 12)   /* Check for Busy State on the DATA0 pin */
#endif

/* SDH_PWR_CTL bitmasks */
#ifndef RSI_BLKSZ
#define PWR_ON             0x3         /* Power On */
#define SD_CMD_OD          (1 << 6)    /* Open Drain Output */
#define ROD_CTL            (1 << 7)    /* Rod Control */
#endif

/* SDH_CLK_CTL bitmasks */
#define CLKDIV             0xff        /* MC_CLK Divisor */
#define CLK_E              (1 << 8)    /* MC_CLK Bus Clock Enable */
#define PWR_SV_E           (1 << 9)    /* Power Save Enable */
#define CLKDIV_BYPASS      (1 << 10)   /* Bypass Divisor */
#define BUS_MODE_MASK      0x1800      /* Bus Mode Mask */
#define STD_BUS_1          0x000       /* Standard Bus 1 bit mode */
#define WIDE_BUS_4         0x800       /* Wide Bus 4 bit mode */
#define BYTE_BUS_8         0x1000      /* Byte Bus 8 bit mode */

/* SDH_RESP_CMD bitmasks */
#define RESP_CMD           0x3f        /* Response Command */

/* SDH_DATA_CTL bitmasks */
#define DTX_E              (1 << 0)    /* Data Transfer Enable */
#define DTX_DIR            (1 << 1)    /* Data Transfer Direction */
#define DTX_MODE           (1 << 2)    /* Data Transfer Mode */
#define DTX_DMA_E          (1 << 3)    /* Data Transfer DMA Enable */
#ifndef RSI_BLKSZ
#define DTX_BLK_LGTH       (0xf << 4)  /* Data Transfer Block Length */
#else

/* Bit masks for SDH_BLK_SIZE */
#define DTX_BLK_LGTH       0x1fff      /* Data Transfer Block Length */
#endif

/* SDH_STATUS bitmasks */
#define CMD_CRC_FAIL       (1 << 0)    /* CMD CRC Fail */
#define DAT_CRC_FAIL       (1 << 1)    /* Data CRC Fail */
#define CMD_TIME_OUT       (1 << 2)    /* CMD Time Out */
#define DAT_TIME_OUT       (1 << 3)    /* Data Time Out */
#define TX_UNDERRUN        (1 << 4)    /* Transmit Underrun */
#define RX_OVERRUN         (1 << 5)    /* Receive Overrun */
#define CMD_RESP_END       (1 << 6)    /* CMD Response End */
#define CMD_SENT           (1 << 7)    /* CMD Sent */
#define DAT_END            (1 << 8)    /* Data End */
#define START_BIT_ERR      (1 << 9)    /* Start Bit Error */
#define DAT_BLK_END        (1 << 10)   /* Data Block End */
#define CMD_ACT            (1 << 11)   /* CMD Active */
#define TX_ACT             (1 << 12)   /* Transmit Active */
#define RX_ACT             (1 << 13)   /* Receive Active */
#define TX_FIFO_STAT       (1 << 14)   /* Transmit FIFO Status */
#define RX_FIFO_STAT       (1 << 15)   /* Receive FIFO Status */
#define TX_FIFO_FULL       (1 << 16)   /* Transmit FIFO Full */
#define RX_FIFO_FULL       (1 << 17)   /* Receive FIFO Full */
#define TX_FIFO_ZERO       (1 << 18)   /* Transmit FIFO Empty */
#define RX_DAT_ZERO        (1 << 19)   /* Receive FIFO Empty */
#define TX_DAT_RDY         (1 << 20)   /* Transmit Data Available */
#define RX_FIFO_RDY        (1 << 21)   /* Receive Data Available */

/* SDH_STATUS_CLR bitmasks */
#define CMD_CRC_FAIL_STAT  (1 << 0)    /* CMD CRC Fail Status */
#define DAT_CRC_FAIL_STAT  (1 << 1)    /* Data CRC Fail Status */
#define CMD_TIMEOUT_STAT   (1 << 2)    /* CMD Time Out Status */
#define DAT_TIMEOUT_STAT   (1 << 3)    /* Data Time Out status */
#define TX_UNDERRUN_STAT   (1 << 4)    /* Transmit Underrun Status */
#define RX_OVERRUN_STAT    (1 << 5)    /* Receive Overrun Status */
#define CMD_RESP_END_STAT  (1 << 6)    /* CMD Response End Status */
#define CMD_SENT_STAT      (1 << 7)    /* CMD Sent Status */
#define DAT_END_STAT       (1 << 8)    /* Data End Status */
#define START_BIT_ERR_STAT (1 << 9)    /* Start Bit Error Status */
#define DAT_BLK_END_STAT   (1 << 10)   /* Data Block End Status */

/* SDH_MASK0 bitmasks */
#define CMD_CRC_FAIL_MASK  (1 << 0)    /* CMD CRC Fail Mask */
#define DAT_CRC_FAIL_MASK  (1 << 1)    /* Data CRC Fail Mask */
#define CMD_TIMEOUT_MASK   (1 << 2)    /* CMD Time Out Mask */
#define DAT_TIMEOUT_MASK   (1 << 3)    /* Data Time Out Mask */
#define TX_UNDERRUN_MASK   (1 << 4)    /* Transmit Underrun Mask */
#define RX_OVERRUN_MASK    (1 << 5)    /* Receive Overrun Mask */
#define CMD_RESP_END_MASK  (1 << 6)    /* CMD Response End Mask */
#define CMD_SENT_MASK      (1 << 7)    /* CMD Sent Mask */
#define DAT_END_MASK       (1 << 8)    /* Data End Mask */
#define START_BIT_ERR_MASK (1 << 9)    /* Start Bit Error Mask */
#define DAT_BLK_END_MASK   (1 << 10)   /* Data Block End Mask */
#define CMD_ACT_MASK       (1 << 11)   /* CMD Active Mask */
#define TX_ACT_MASK        (1 << 12)   /* Transmit Active Mask */
#define RX_ACT_MASK        (1 << 13)   /* Receive Active Mask */
#define TX_FIFO_STAT_MASK  (1 << 14)   /* Transmit FIFO Status Mask */
#define RX_FIFO_STAT_MASK  (1 << 15)   /* Receive FIFO Status Mask */
#define TX_FIFO_FULL_MASK  (1 << 16)   /* Transmit FIFO Full Mask */
#define RX_FIFO_FULL_MASK  (1 << 17)   /* Receive FIFO Full Mask */
#define TX_FIFO_ZERO_MASK  (1 << 18)   /* Transmit FIFO Empty Mask */
#define RX_DAT_ZERO_MASK   (1 << 19)   /* Receive FIFO Empty Mask */
#define TX_DAT_RDY_MASK    (1 << 20)   /* Transmit Data Available Mask */
#define RX_FIFO_RDY_MASK   (1 << 21)   /* Receive Data Available Mask */

/* SDH_FIFO_CNT bitmasks */
#define FIFO_COUNT         0x7fff      /* FIFO Count */

/* SDH_E_STATUS bitmasks */
#define SDIO_INT_DET       (1 << 1)    /* SDIO Int Detected */
#define SD_CARD_DET        (1 << 4)    /* SD Card Detect */
#define SD_CARD_BUSYMODE   (1 << 31)   /* Card is in Busy mode */
#define SD_CARD_SLPMODE    (1 << 30)   /* Card in Sleep Mode */
#define SD_CARD_READY      (1 << 17)   /* Card Ready */

/* SDH_E_MASK bitmasks */
#define SDIO_MSK           (1 << 1)    /* Mask SDIO Int Detected */
#define SCD_MSK            (1 << 4)    /* Mask Card Detect */
#define CARD_READY_MSK     (1 << 16)   /* Mask Card Ready */

/* SDH_CFG bitmasks */
#define CLKS_EN            (1 << 0)    /* Clocks Enable */
#define SD4E               (1 << 2)    /* SDIO 4-Bit Enable */
#define MWE                (1 << 3)    /* Moving Window Enable */
#define SD_RST             (1 << 4)    /* SDMMC Reset */
#define PUP_SDDAT          (1 << 5)    /* Pull-up SD_DAT */
#define PUP_SDDAT3         (1 << 6)    /* Pull-up SD_DAT3 */
#ifndef RSI_BLKSZ
#define PD_SDDAT3          (1 << 7)    /* Pull-down SD_DAT3 */
#else
#define PWR_ON             0x600       /* Power On */
#define SD_CMD_OD          (1 << 11)   /* Open Drain Output */
#define BOOT_EN            (1 << 12)   /* Boot Enable */
#define BOOT_MODE          (1 << 13)   /* Alternate Boot Mode */
#define BOOT_ACK_EN        (1 << 14)   /* Boot ACK is expected */
#endif

/* SDH_RD_WAIT_EN bitmasks */
#define RWR                (1 << 0)    /* Read Wait Request */

#endif