OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:12 AM	rwxr-xr-x
📄 Kbuild	681 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 arcregs.h	8.59 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 asm-offsets.h	311 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	15.14 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 barrier.h	1.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	9.81 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bug.h	938 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 cache.h	3.77 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cacheflush.h	3.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	2.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	5.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 current.h	695 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	1.99 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 disasm.h	3.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	734 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	459 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dwarf.h	892 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	2.15 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 entry-arcv2.h	4.85 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 entry-compact.h	9.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry.h	6.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	410 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	411 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	3.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugepage.h	2.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	6.43 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 irq.h	825 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags-arcv2.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags-compact.h	4.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	509 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	400 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	489 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	1.42 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mach_desc.h	2.06 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu.h	2.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	5.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	989 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	661 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	2.99 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pci.h	705 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	6.86 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pgalloc.h	3.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	14.2 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 processor.h	4.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	3.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	407 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 segment.h	612 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	644 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	442 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	4.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	8.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	1.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscalls.h	653 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	3.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	508 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb-mmu1.h	3.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	1.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	18.45 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 unaligned.h	771 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unwind.h	3.51 KB	01/28/2018 09:20:33 PM	rw-r--r--

Name

Size

Modified

Perms

📁 ..

05/09/2024 07:14:12 AM

rwxr-xr-x

📄 Kbuild

681 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 arcregs.h

8.59 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 asm-offsets.h

311 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 atomic.h

15.14 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 barrier.h

1.75 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bitops.h

9.81 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 bug.h

938 bytes

06/16/2023 05:32:39 PM

rw-r--r--

📄 cache.h

3.77 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 cacheflush.h

3.88 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 checksum.h

2.45 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cmpxchg.h

5.4 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 current.h

695 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 delay.h

1.99 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 disasm.h

3.87 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma-mapping.h

734 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma.h

459 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 dwarf.h

892 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 elf.h

2.15 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 entry-arcv2.h

4.85 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 entry-compact.h

9.29 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 entry.h

6.73 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 exec.h

410 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 fb.h

411 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 futex.h

3.67 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 highmem.h

1.46 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hugepage.h

2.41 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 io.h

6.43 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 irq.h

825 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 irqflags-arcv2.h

3.45 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irqflags-compact.h

4.25 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irqflags.h

509 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 kdebug.h

400 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 kgdb.h

1.35 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 kmap_types.h

489 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 kprobes.h

1.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 linkage.h

1.42 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 mach_desc.h

2.06 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 mmu.h

2.44 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu_context.h

5.67 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmzone.h

989 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 module.h

661 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 page.h

2.99 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 pci.h

705 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 perf_event.h

6.86 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 pgalloc.h

3.79 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgtable.h

14.2 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 processor.h

4.69 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 ptrace.h

3.87 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 sections.h

407 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 segment.h

612 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 serial.h

644 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 setup.h

1.18 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 shmparam.h

442 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 smp.h

4.25 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock.h

8.79 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock_types.h

1.03 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 stacktrace.h

1.29 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 string.h

1.15 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 switch_to.h

1.17 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 syscall.h

1.57 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 syscalls.h

653 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 thread_info.h

3.39 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 timex.h

508 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlb-mmu1.h

3.48 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlb.h

1.23 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlbflush.h

1.76 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 uaccess.h

18.45 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 unaligned.h

771 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 unwind.h

3.51 KB

01/28/2018 09:20:33 PM

rw-r--r--

Editing: cache.h

/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __ARC_ASM_CACHE_H
#define __ARC_ASM_CACHE_H

/* In case $$ not config, setup a dummy number for rest of kernel */
#ifndef CONFIG_ARC_CACHE_LINE_SHIFT
#define L1_CACHE_SHIFT		6
#else
#define L1_CACHE_SHIFT		CONFIG_ARC_CACHE_LINE_SHIFT
#endif

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
#define CACHE_LINE_MASK		(~(L1_CACHE_BYTES - 1))

/*
 * ARC700 doesn't cache any access in top 1G (0xc000_0000 to 0xFFFF_FFFF)
 * Ideal for wiring memory mapped peripherals as we don't need to do
 * explicit uncached accesses (LD.di/ST.di) hence more portable drivers
 */
#define ARC_UNCACHED_ADDR_SPACE	0xc0000000

#ifndef __ASSEMBLY__

/* Uncached access macros */
#define arc_read_uncached_32(ptr)	\
({					\
	unsigned int __ret;		\
	__asm__ __volatile__(		\
	"	ld.di %0, [%1]	\n"	\
	: "=r"(__ret)			\
	: "r"(ptr));			\
	__ret;				\
})

#define arc_write_uncached_32(ptr, data)\
({					\
	__asm__ __volatile__(		\
	"	st.di %0, [%1]	\n"	\
	:				\
	: "r"(data), "r"(ptr));		\
})

/* Largest line length for either L1 or L2 is 128 bytes */
#define SMP_CACHE_BYTES		128
#define cache_line_size()	SMP_CACHE_BYTES
#define ARCH_DMA_MINALIGN	SMP_CACHE_BYTES

/*
 * Make sure slab-allocated buffers are 64-bit aligned when atomic64_t uses
 * ARCv2 64-bit atomics (LLOCKD/SCONDD). This guarantess runtime 64-bit
 * alignment for any atomic64_t embedded in buffer.
 * Default ARCH_SLAB_MINALIGN is __alignof__(long long) which has a relaxed
 * value of 4 (and not 8) in ARC ABI.
 */
#if defined(CONFIG_ARC_HAS_LL64) && defined(CONFIG_ARC_HAS_LLSC)
#define ARCH_SLAB_MINALIGN	8
#endif

extern void arc_cache_init(void);
extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
extern void read_decode_cache_bcr(void);

extern int ioc_enable;
extern unsigned long perip_base, perip_end;

#endif	/* !__ASSEMBLY__ */

/* Instruction cache related Auxiliary registers */
#define ARC_REG_IC_BCR		0x77	/* Build Config reg */
#define ARC_REG_IC_IVIC		0x10
#define ARC_REG_IC_CTRL		0x11
#define ARC_REG_IC_IVIR		0x16
#define ARC_REG_IC_ENDR		0x17
#define ARC_REG_IC_IVIL		0x19
#define ARC_REG_IC_PTAG		0x1E
#define ARC_REG_IC_PTAG_HI	0x1F

/* Bit val in IC_CTRL */
#define IC_CTRL_DIS		0x1

/* Data cache related Auxiliary registers */
#define ARC_REG_DC_BCR		0x72	/* Build Config reg */
#define ARC_REG_DC_IVDC		0x47
#define ARC_REG_DC_CTRL		0x48
#define ARC_REG_DC_IVDL		0x4A
#define ARC_REG_DC_FLSH		0x4B
#define ARC_REG_DC_FLDL		0x4C
#define ARC_REG_DC_STARTR	0x4D
#define ARC_REG_DC_ENDR		0x4E
#define ARC_REG_DC_PTAG		0x5C
#define ARC_REG_DC_PTAG_HI	0x5F

/* Bit val in DC_CTRL */
#define DC_CTRL_DIS		0x001
#define DC_CTRL_INV_MODE_FLUSH	0x040
#define DC_CTRL_FLUSH_STATUS	0x100
#define DC_CTRL_RGN_OP_INV	0x200
#define DC_CTRL_RGN_OP_MSK	0x200

/*System-level cache (L2 cache) related Auxiliary registers */
#define ARC_REG_SLC_CFG		0x901
#define ARC_REG_SLC_CTRL	0x903
#define ARC_REG_SLC_FLUSH	0x904
#define ARC_REG_SLC_INVALIDATE	0x905
#define ARC_AUX_SLC_IVDL	0x910
#define ARC_AUX_SLC_FLDL	0x912
#define ARC_REG_SLC_RGN_START	0x914
#define ARC_REG_SLC_RGN_START1	0x915
#define ARC_REG_SLC_RGN_END	0x916
#define ARC_REG_SLC_RGN_END1	0x917

/* Bit val in SLC_CONTROL */
#define SLC_CTRL_DIS		0x001
#define SLC_CTRL_IM		0x040
#define SLC_CTRL_BUSY		0x100
#define SLC_CTRL_RGN_OP_INV	0x200

/* IO coherency related Auxiliary registers */
#define ARC_REG_IO_COH_ENABLE	0x500
#define ARC_IO_COH_ENABLE_BIT	BIT(0)
#define ARC_REG_IO_COH_PARTIAL	0x501
#define ARC_IO_COH_PARTIAL_BIT	BIT(0)
#define ARC_REG_IO_COH_AP0_BASE	0x508
#define ARC_REG_IO_COH_AP0_SIZE	0x509

#endif /* _ASM_CACHE_H */