OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 8xx_immap.h	13.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 Kbuild	248 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 accounting.h	1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 agp.h	525 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 archrandom.h	1016 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 asm-compat.h	2.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	4.78 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 async_tx.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	13.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 backlight.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	3.57 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	7.8 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 book3s	-	11/17/2022 06:42:21 AM	rwxr-xr-x
📄 bootx.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 btext.h	926 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	3.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	486 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	2.47 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cacheflush.h	3.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cell-pmu.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cell-regs.h	9.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	5.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	12.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 code-patching-asm.h	397 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 code-patching.h	5.01 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compat.h	6.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 context_tracking.h	245 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 copro.h	769 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpm.h	5.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpm1.h	21.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpm2.h	48.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu_has_feature.h	1.31 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpufeature.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpuidle.h	3.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cputable.h	22.56 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cputhreads.h	2.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cputime.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	835 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dbdma.h	3.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dbell.h	2.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr-generic.h	1.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr-mmio.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr-native.h	4.42 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dcr-regs.h	5.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug.h	1.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debugfs.h	489 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	3.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 disassemble.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	4.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	10.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dt_cpu_ftrs.h	816 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 edac.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeh.h	14.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeh_event.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ehv_pic.h	963 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	6.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emergency-restart.h	43 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 emulated_ops.h	2.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 epapr_hcalls.h	16.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exception-64e.h	7.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exception-64s.h	22.72 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 exec.h	246 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	904 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fadump.h	6.1 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 fb.h	483 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 feature-fixups.h	8.76 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 firmware.h	4.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	4.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs_pd.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_85xx_cache_sram.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_gtm.h	1.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_hcalls.h	17.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_lbc.h	10.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_pamu_stash.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_pm.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 grackle.h	331 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 head-64.h	13.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 heathrow.h	2.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	2.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hmi.h	1.49 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hugetlb.h	4.73 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hvcall.h	15.35 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hvconsole.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hvcserver.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hvsi.h	2.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	5.24 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hydra.h	2.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8259.h	361 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ibmebus.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 icswx.h	4.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	586 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ima.h	772 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 imc-pmu.h	2.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 immap_cpm2.h	10.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-defs.h	3.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-workarounds.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	28.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 io_event_irq.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu.h	10.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipic.h	3.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_work.h	252 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 irqflags.h	1.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 isa-bridge.h	654 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	291 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdump.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	4.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 keylargo.h	10.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	2.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	434 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	3.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kup.h	1021 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_asm.h	5.46 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_book3s.h	12.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_book3s_32.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_book3s_64.h	12.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_book3s_asm.h	4.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_booke.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_booke_hv_asm.h	2.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_fpu.h	2.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_host.h	19.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_para.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_ppc.h	34.83 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 libata-portmap.h	249 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	501 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 livepatch.h	1.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 local.h	3.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lppaca.h	5.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lv1call.h	18.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 machdep.h	9.7 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 macio.h	3.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	943 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mce.h	5.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mediabay.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mm-arch-hooks.h	839 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mman.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu-40x.h	1.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu-44x.h	5.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu-8xx.h	8.6 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmu-book3e.h	9.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	9.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	6.26 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmzone.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	2.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc5121.h	3.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc52xx.h	10.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc52xx_psc.h	9.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc5xxx.h	641 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc6xx.h	143 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc8260.h	742 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc85xx.h	2.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpic.h	13.97 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mpic_msgr.h	3.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpic_timer.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msi_bitmap.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nmi.h	238 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📁 nohash	-	11/17/2022 06:42:21 AM	rwxr-xr-x
📄 nvram.h	3.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ohare.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 opal-api.h	29.34 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 opal.h	16.53 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 oprofile_impl.h	3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 paca.h	8.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page.h	10.65 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page_32.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_64.h	2.93 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 parport.h	956 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pasemi_dma.h	23.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-bridge.h	9.21 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci.h	4.58 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 percpu.h	468 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 perf_event.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event_fsl_emb.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event_server.h	6.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	620 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-be-types.h	2.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-types.h	1.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	2.45 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 plpar_wrappers.h	8.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmac_feature.h	13.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmac_low_i2c.h	3.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmac_pfunc.h	8.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmc.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmi.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pnv-ocxl.h	1.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pnv-pci.h	3.22 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 powernv.h	1.57 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ppc-opcode.h	19.05 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ppc-pci.h	2.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppc4xx.h	530 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppc4xx_ocm.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppc_asm.h	21.63 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 probes.h	2.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	15 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 prom.h	7.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ps3.h	15.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ps3av.h	23.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ps3gpu.h	2.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ps3stor.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pte-common.h	6.27 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pte-walk.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	7.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg.h	61.61 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 reg_8xx.h	4.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg_a2.h	6.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg_booke.h	36.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 reg_fsl_emb.h	3.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rheap.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rio.h	637 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rtas.h	14.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 runlatch.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scom.h	4.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	249 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 security_features.h	3.03 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 serial.h	677 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setjmp.h	630 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 setup.h	2.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sfp-machine.h	12.38 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 shmparam.h	206 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	225 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 slice.h	1.12 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 smp.h	6.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 smu.h	19.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	7.04 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 spinlock_types.h	424 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spu.h	25.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spu_csa.h	6.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
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Editing: fsl_lbc.h

/* Freescale Local Bus Controller
 *
 * Copyright © 2006-2007, 2010 Freescale Semiconductor
 *
 * Authors: Nick Spence <nick.spence@freescale.com>,
 *          Scott Wood <scottwood@freescale.com>
 *          Jack Lan <jack.lan@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#ifndef __ASM_FSL_LBC_H
#define __ASM_FSL_LBC_H

#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/io.h>
#include <linux/device.h>
#include <linux/spinlock.h>

struct fsl_lbc_bank {
	__be32 br;             /**< Base Register  */
#define BR_BA           0xFFFF8000
#define BR_BA_SHIFT             15
#define BR_PS           0x00001800
#define BR_PS_SHIFT             11
#define BR_PS_8         0x00000800  /* Port Size 8 bit */
#define BR_PS_16        0x00001000  /* Port Size 16 bit */
#define BR_PS_32        0x00001800  /* Port Size 32 bit */
#define BR_DECC         0x00000600
#define BR_DECC_SHIFT            9
#define BR_DECC_OFF     0x00000000  /* HW ECC checking and generation off */
#define BR_DECC_CHK     0x00000200  /* HW ECC checking on, generation off */
#define BR_DECC_CHK_GEN 0x00000400  /* HW ECC checking and generation on */
#define BR_WP           0x00000100
#define BR_WP_SHIFT              8
#define BR_MSEL         0x000000E0
#define BR_MSEL_SHIFT            5
#define BR_MS_GPCM      0x00000000  /* GPCM */
#define BR_MS_FCM       0x00000020  /* FCM */
#define BR_MS_SDRAM     0x00000060  /* SDRAM */
#define BR_MS_UPMA      0x00000080  /* UPMA */
#define BR_MS_UPMB      0x000000A0  /* UPMB */
#define BR_MS_UPMC      0x000000C0  /* UPMC */
#define BR_V            0x00000001
#define BR_V_SHIFT               0
#define BR_RES          ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)

__be32 or;             /**< Base Register  */
#define OR0 0x5004
#define OR1 0x500C
#define OR2 0x5014
#define OR3 0x501C
#define OR4 0x5024
#define OR5 0x502C
#define OR6 0x5034
#define OR7 0x503C

#define OR_FCM_AM               0xFFFF8000
#define OR_FCM_AM_SHIFT                 15
#define OR_FCM_BCTLD            0x00001000
#define OR_FCM_BCTLD_SHIFT              12
#define OR_FCM_PGS              0x00000400
#define OR_FCM_PGS_SHIFT                10
#define OR_FCM_CSCT             0x00000200
#define OR_FCM_CSCT_SHIFT                9
#define OR_FCM_CST              0x00000100
#define OR_FCM_CST_SHIFT                 8
#define OR_FCM_CHT              0x00000080
#define OR_FCM_CHT_SHIFT                 7
#define OR_FCM_SCY              0x00000070
#define OR_FCM_SCY_SHIFT                 4
#define OR_FCM_SCY_1            0x00000010
#define OR_FCM_SCY_2            0x00000020
#define OR_FCM_SCY_3            0x00000030
#define OR_FCM_SCY_4            0x00000040
#define OR_FCM_SCY_5            0x00000050
#define OR_FCM_SCY_6            0x00000060
#define OR_FCM_SCY_7            0x00000070
#define OR_FCM_RST              0x00000008
#define OR_FCM_RST_SHIFT                 3
#define OR_FCM_TRLX             0x00000004
#define OR_FCM_TRLX_SHIFT                2
#define OR_FCM_EHTR             0x00000002
#define OR_FCM_EHTR_SHIFT                1

#define OR_GPCM_AM		0xFFFF8000
#define OR_GPCM_AM_SHIFT		15
};

struct fsl_lbc_regs {
	struct fsl_lbc_bank bank[12];
	u8 res0[0x8];
	__be32 mar;             /**< UPM Address Register */
	u8 res1[0x4];
	__be32 mamr;            /**< UPMA Mode Register */
#define MxMR_OP_NO	(0 << 28) /**< normal operation */
#define MxMR_OP_WA	(1 << 28) /**< write array */
#define MxMR_OP_RA	(2 << 28) /**< read array */
#define MxMR_OP_RP	(3 << 28) /**< run pattern */
#define MxMR_MAD	0x3f      /**< machine address */
	__be32 mbmr;            /**< UPMB Mode Register */
	__be32 mcmr;            /**< UPMC Mode Register */
	u8 res2[0x8];
	__be32 mrtpr;           /**< Memory Refresh Timer Prescaler Register */
	__be32 mdr;             /**< UPM Data Register */
	u8 res3[0x4];
	__be32 lsor;            /**< Special Operation Initiation Register */
	__be32 lsdmr;           /**< SDRAM Mode Register */
	u8 res4[0x8];
	__be32 lurt;            /**< UPM Refresh Timer */
	__be32 lsrt;            /**< SDRAM Refresh Timer */
	u8 res5[0x8];
	__be32 ltesr;           /**< Transfer Error Status Register */
#define LTESR_BM   0x80000000
#define LTESR_FCT  0x40000000
#define LTESR_PAR  0x20000000
#define LTESR_WP   0x04000000
#define LTESR_ATMW 0x00800000
#define LTESR_ATMR 0x00400000
#define LTESR_CS   0x00080000
#define LTESR_UPM  0x00000002
#define LTESR_CC   0x00000001
#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
#define LTESR_MASK      (LTESR_BM | LTESR_FCT | LTESR_PAR | LTESR_WP \
			 | LTESR_ATMW | LTESR_ATMR | LTESR_CS | LTESR_UPM \
			 | LTESR_CC)
#define LTESR_CLEAR	0xFFFFFFFF
#define LTECCR_CLEAR	0xFFFFFFFF
#define LTESR_STATUS	LTESR_MASK
#define LTEIR_ENABLE	LTESR_MASK
#define LTEDR_ENABLE	0x00000000
	__be32 ltedr;           /**< Transfer Error Disable Register */
	__be32 lteir;           /**< Transfer Error Interrupt Register */
	__be32 lteatr;          /**< Transfer Error Attributes Register */
	__be32 ltear;           /**< Transfer Error Address Register */
	__be32 lteccr;          /**< Transfer Error ECC Register */
	u8 res6[0x8];
	__be32 lbcr;            /**< Configuration Register */
#define LBCR_LDIS  0x80000000
#define LBCR_LDIS_SHIFT    31
#define LBCR_BCTLC 0x00C00000
#define LBCR_BCTLC_SHIFT   22
#define LBCR_AHD   0x00200000
#define LBCR_LPBSE 0x00020000
#define LBCR_LPBSE_SHIFT   17
#define LBCR_EPAR  0x00010000
#define LBCR_EPAR_SHIFT    16
#define LBCR_BMT   0x0000FF00
#define LBCR_BMT_SHIFT      8
#define LBCR_BMTPS 0x0000000F
#define LBCR_BMTPS_SHIFT    0
#define LBCR_INIT  0x00040000
	__be32 lcrr;            /**< Clock Ratio Register */
#define LCRR_DBYP    0x80000000
#define LCRR_DBYP_SHIFT      31
#define LCRR_BUFCMDC 0x30000000
#define LCRR_BUFCMDC_SHIFT   28
#define LCRR_ECL     0x03000000
#define LCRR_ECL_SHIFT       24
#define LCRR_EADC    0x00030000
#define LCRR_EADC_SHIFT      16
#define LCRR_CLKDIV  0x0000000F
#define LCRR_CLKDIV_SHIFT     0
	u8 res7[0x8];
	__be32 fmr;             /**< Flash Mode Register */
#define FMR_CWTO     0x0000F000
#define FMR_CWTO_SHIFT       12
#define FMR_BOOT     0x00000800
#define FMR_ECCM     0x00000100
#define FMR_AL       0x00000030
#define FMR_AL_SHIFT          4
#define FMR_OP       0x00000003
#define FMR_OP_SHIFT          0
	__be32 fir;             /**< Flash Instruction Register */
#define FIR_OP0      0xF0000000
#define FIR_OP0_SHIFT        28
#define FIR_OP1      0x0F000000
#define FIR_OP1_SHIFT        24
#define FIR_OP2      0x00F00000
#define FIR_OP2_SHIFT        20
#define FIR_OP3      0x000F0000
#define FIR_OP3_SHIFT        16
#define FIR_OP4      0x0000F000
#define FIR_OP4_SHIFT        12
#define FIR_OP5      0x00000F00
#define FIR_OP5_SHIFT         8
#define FIR_OP6      0x000000F0
#define FIR_OP6_SHIFT         4
#define FIR_OP7      0x0000000F
#define FIR_OP7_SHIFT         0
#define FIR_OP_NOP   0x0	/* No operation and end of sequence */
#define FIR_OP_CA    0x1        /* Issue current column address */
#define FIR_OP_PA    0x2        /* Issue current block+page address */
#define FIR_OP_UA    0x3        /* Issue user defined address */
#define FIR_OP_CM0   0x4        /* Issue command from FCR[CMD0] */
#define FIR_OP_CM1   0x5        /* Issue command from FCR[CMD1] */
#define FIR_OP_CM2   0x6        /* Issue command from FCR[CMD2] */
#define FIR_OP_CM3   0x7        /* Issue command from FCR[CMD3] */
#define FIR_OP_WB    0x8        /* Write FBCR bytes from FCM buffer */
#define FIR_OP_WS    0x9        /* Write 1 or 2 bytes from MDR[AS] */
#define FIR_OP_RB    0xA        /* Read FBCR bytes to FCM buffer */
#define FIR_OP_RS    0xB        /* Read 1 or 2 bytes to MDR[AS] */
#define FIR_OP_CW0   0xC        /* Wait then issue FCR[CMD0] */
#define FIR_OP_CW1   0xD        /* Wait then issue FCR[CMD1] */
#define FIR_OP_RBW   0xE        /* Wait then read FBCR bytes */
#define FIR_OP_RSW   0xE        /* Wait then read 1 or 2 bytes */
	__be32 fcr;             /**< Flash Command Register */
#define FCR_CMD0     0xFF000000
#define FCR_CMD0_SHIFT       24
#define FCR_CMD1     0x00FF0000
#define FCR_CMD1_SHIFT       16
#define FCR_CMD2     0x0000FF00
#define FCR_CMD2_SHIFT        8
#define FCR_CMD3     0x000000FF
#define FCR_CMD3_SHIFT        0
	__be32 fbar;            /**< Flash Block Address Register */
#define FBAR_BLK     0x00FFFFFF
	__be32 fpar;            /**< Flash Page Address Register */
#define FPAR_SP_PI   0x00007C00
#define FPAR_SP_PI_SHIFT     10
#define FPAR_SP_MS   0x00000200
#define FPAR_SP_CI   0x000001FF
#define FPAR_SP_CI_SHIFT      0
#define FPAR_LP_PI   0x0003F000
#define FPAR_LP_PI_SHIFT     12
#define FPAR_LP_MS   0x00000800
#define FPAR_LP_CI   0x000007FF
#define FPAR_LP_CI_SHIFT      0
	__be32 fbcr;            /**< Flash Byte Count Register */
#define FBCR_BC      0x00000FFF
};

/*
 * FSL UPM routines
 */
struct fsl_upm {
	__be32 __iomem *mxmr;
	int width;
};

extern u32 fsl_lbc_addr(phys_addr_t addr_base);
extern int fsl_lbc_find(phys_addr_t addr_base);
extern int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm);

/**
 * fsl_upm_start_pattern - start UPM patterns execution
 * @upm:	pointer to the fsl_upm structure obtained via fsl_upm_find
 * @pat_offset:	UPM pattern offset for the command to be executed
 *
 * This routine programmes UPM so the next memory access that hits an UPM
 * will trigger pattern execution, starting at pat_offset.
 */
static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
{
	clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset);
}

/**
 * fsl_upm_end_pattern - end UPM patterns execution
 * @upm:	pointer to the fsl_upm structure obtained via fsl_upm_find
 *
 * This routine reverts UPM to normal operation mode.
 */
static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
{
	clrbits32(upm->mxmr, MxMR_OP_RP);

while (in_be32(upm->mxmr) & MxMR_OP_RP)
		cpu_relax();
}

/* overview of the fsl lbc controller */

struct fsl_lbc_ctrl {
	/* device info */
	struct device			*dev;
	struct fsl_lbc_regs __iomem	*regs;
	int				irq[2];
	wait_queue_head_t		irq_wait;
	spinlock_t			lock;
	void				*nand;

/* status read from LTESR by irq handler */
	unsigned int			irq_status;

#ifdef CONFIG_SUSPEND
	/* save regs when system go to deep-sleep */
	struct fsl_lbc_regs		*saved_regs;
#endif
};

extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
			       u32 mar);
extern struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;

#endif /* __ASM_FSL_LBC_H */