OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 8xx_immap.h	13.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 Kbuild	248 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 accounting.h	1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 agp.h	525 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 archrandom.h	1016 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 asm-compat.h	2.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	4.78 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 async_tx.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	13.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 backlight.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	3.57 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	7.8 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 book3s	-	11/17/2022 06:42:21 AM	rwxr-xr-x
📄 bootx.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 btext.h	926 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	3.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	486 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	2.47 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cacheflush.h	3.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cell-pmu.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cell-regs.h	9.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	5.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	12.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 code-patching-asm.h	397 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 code-patching.h	5.01 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compat.h	6.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 context_tracking.h	245 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 copro.h	769 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpm.h	5.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpm1.h	21.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpm2.h	48.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu_has_feature.h	1.31 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpufeature.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpuidle.h	3.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cputable.h	22.56 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cputhreads.h	2.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cputime.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	835 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dbdma.h	3.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dbell.h	2.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr-generic.h	1.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr-mmio.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr-native.h	4.42 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dcr-regs.h	5.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug.h	1.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debugfs.h	489 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	3.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 disassemble.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	4.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	10.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dt_cpu_ftrs.h	816 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 edac.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeh.h	14.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeh_event.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ehv_pic.h	963 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	6.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emergency-restart.h	43 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 emulated_ops.h	2.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 epapr_hcalls.h	16.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exception-64e.h	7.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exception-64s.h	22.72 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 exec.h	246 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	904 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fadump.h	6.1 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 fb.h	483 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 feature-fixups.h	8.76 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 firmware.h	4.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	4.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs_pd.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_85xx_cache_sram.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_gtm.h	1.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_hcalls.h	17.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_lbc.h	10.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_pamu_stash.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_pm.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 grackle.h	331 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 head-64.h	13.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 heathrow.h	2.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	2.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hmi.h	1.49 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hugetlb.h	4.73 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hvcall.h	15.35 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hvconsole.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hvcserver.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hvsi.h	2.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	5.24 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hydra.h	2.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8259.h	361 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ibmebus.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 icswx.h	4.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	586 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ima.h	772 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 imc-pmu.h	2.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 immap_cpm2.h	10.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-defs.h	3.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-workarounds.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	28.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 io_event_irq.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu.h	10.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipic.h	3.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_work.h	252 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 irqflags.h	1.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 isa-bridge.h	654 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	291 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdump.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	4.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 keylargo.h	10.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	2.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	434 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	3.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kup.h	1021 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_asm.h	5.46 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_book3s.h	12.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_book3s_32.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_book3s_64.h	12.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_book3s_asm.h	4.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_booke.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_booke_hv_asm.h	2.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_fpu.h	2.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_host.h	19.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_para.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_ppc.h	34.83 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 libata-portmap.h	249 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	501 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 livepatch.h	1.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 local.h	3.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lppaca.h	5.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lv1call.h	18.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 machdep.h	9.7 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 macio.h	3.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	943 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mce.h	5.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mediabay.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mm-arch-hooks.h	839 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mman.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu-40x.h	1.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu-44x.h	5.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu-8xx.h	8.6 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmu-book3e.h	9.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	9.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	6.26 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmzone.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	2.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc5121.h	3.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc52xx.h	10.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc52xx_psc.h	9.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc5xxx.h	641 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc6xx.h	143 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc8260.h	742 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc85xx.h	2.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpic.h	13.97 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mpic_msgr.h	3.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpic_timer.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msi_bitmap.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nmi.h	238 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📁 nohash	-	11/17/2022 06:42:21 AM	rwxr-xr-x
📄 nvram.h	3.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ohare.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 opal-api.h	29.34 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 opal.h	16.53 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 oprofile_impl.h	3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 paca.h	8.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page.h	10.65 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page_32.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_64.h	2.93 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 parport.h	956 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pasemi_dma.h	23.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-bridge.h	9.21 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci.h	4.58 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 percpu.h	468 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 perf_event.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event_fsl_emb.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event_server.h	6.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	620 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-be-types.h	2.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-types.h	1.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	2.45 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 plpar_wrappers.h	8.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmac_feature.h	13.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmac_low_i2c.h	3.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmac_pfunc.h	8.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmc.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmi.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pnv-ocxl.h	1.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pnv-pci.h	3.22 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 powernv.h	1.57 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ppc-opcode.h	19.05 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ppc-pci.h	2.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppc4xx.h	530 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppc4xx_ocm.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppc_asm.h	21.63 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 probes.h	2.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	15 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 prom.h	7.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ps3.h	15.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ps3av.h	23.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ps3gpu.h	2.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ps3stor.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pte-common.h	6.27 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pte-walk.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	7.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg.h	61.61 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 reg_8xx.h	4.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg_a2.h	6.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg_booke.h	36.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 reg_fsl_emb.h	3.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rheap.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rio.h	637 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rtas.h	14.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 runlatch.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scom.h	4.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	249 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 security_features.h	3.03 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 serial.h	677 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setjmp.h	630 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 setup.h	2.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sfp-machine.h	12.38 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 shmparam.h	206 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	225 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 slice.h	1.12 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 smp.h	6.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 smu.h	19.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	7.04 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 spinlock_types.h	424 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spu.h	25.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spu_csa.h	6.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
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Editing: dma.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_POWERPC_DMA_H
#define _ASM_POWERPC_DMA_H
#ifdef __KERNEL__

/*
 * Defines for using and allocating dma channels.
 * Written by Hennus Bergman, 1992.
 * High DMA channel support & info by Hannu Savolainen
 * and John Boyd, Nov. 1992.
 * Changes for ppc sound by Christoph Nadig
 */

/*
 * Note: Adapted for PowerPC by Gary Thomas
 * Modified by Cort Dougan <cort@cs.nmt.edu>
 *
 * None of this really applies for Power Macintoshes.  There is
 * basically just enough here to get kernel/dma.c to compile.
 */

#include <asm/io.h>
#include <linux/spinlock.h>

#ifndef MAX_DMA_CHANNELS
#define MAX_DMA_CHANNELS	8
#endif

/* The maximum address that we can perform a DMA transfer to on this platform */
/* Doesn't really apply... */
#define MAX_DMA_ADDRESS		(~0UL)

#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
#define dma_outb	outb_p
#else
#define dma_outb	outb
#endif

#define dma_inb		inb

/*
 * NOTES about DMA transfers:
 *
 *  controller 1: channels 0-3, byte operations, ports 00-1F
 *  controller 2: channels 4-7, word operations, ports C0-DF
 *
 *  - ALL registers are 8 bits only, regardless of transfer size
 *  - channel 4 is not used - cascades 1 into 2.
 *  - channels 0-3 are byte - addresses/counts are for physical bytes
 *  - channels 5-7 are word - addresses/counts are for physical words
 *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
 *  - transfer count loaded to registers is 1 less than actual count
 *  - controller 2 offsets are all even (2x offsets for controller 1)
 *  - page registers for 5-7 don't use data bit 0, represent 128K pages
 *  - page registers for 0-3 use bit 0, represent 64K pages
 *
 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
 * Note that addresses loaded into registers must be _physical_ addresses,
 * not logical addresses (which may differ if paging is active).
 *
 *  Address mapping for channels 0-3:
 *
 *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
 *    |  ...  |   |  ... |   |  ... |
 *    |  ...  |   |  ... |   |  ... |
 *    |  ...  |   |  ... |   |  ... |
 *   P7  ...  P0  A7 ... A0  A7 ... A0
 * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
 *
 *  Address mapping for channels 5-7:
 *
 *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
 *    |  ...  |   \   \   ... \  \  \  ... \  \
 *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
 *    |  ...  |     \   \   ... \  \  \  ... \
 *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
 * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
 *
 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
 * the hardware level, so odd-byte transfers aren't possible).
 *
 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
 * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
 *
 */

/* 8237 DMA controllers */
#define IO_DMA1_BASE	0x00	/* 8 bit slave DMA, channels 0..3 */
#define IO_DMA2_BASE	0xC0	/* 16 bit master DMA, ch 4(=slave input)..7 */

/* DMA controller registers */
#define DMA1_CMD_REG		0x08	/* command register (w) */
#define DMA1_STAT_REG		0x08	/* status register (r) */
#define DMA1_REQ_REG		0x09	/* request register (w) */
#define DMA1_MASK_REG		0x0A	/* single-channel mask (w) */
#define DMA1_MODE_REG		0x0B	/* mode register (w) */
#define DMA1_CLEAR_FF_REG	0x0C	/* clear pointer flip-flop (w) */
#define DMA1_TEMP_REG		0x0D	/* Temporary Register (r) */
#define DMA1_RESET_REG		0x0D	/* Master Clear (w) */
#define DMA1_CLR_MASK_REG	0x0E	/* Clear Mask */
#define DMA1_MASK_ALL_REG	0x0F	/* all-channels mask (w) */

#define DMA2_CMD_REG		0xD0	/* command register (w) */
#define DMA2_STAT_REG		0xD0	/* status register (r) */
#define DMA2_REQ_REG		0xD2	/* request register (w) */
#define DMA2_MASK_REG		0xD4	/* single-channel mask (w) */
#define DMA2_MODE_REG		0xD6	/* mode register (w) */
#define DMA2_CLEAR_FF_REG	0xD8	/* clear pointer flip-flop (w) */
#define DMA2_TEMP_REG		0xDA	/* Temporary Register (r) */
#define DMA2_RESET_REG		0xDA	/* Master Clear (w) */
#define DMA2_CLR_MASK_REG	0xDC	/* Clear Mask */
#define DMA2_MASK_ALL_REG	0xDE	/* all-channels mask (w) */

#define DMA_ADDR_0		0x00	/* DMA address registers */
#define DMA_ADDR_1		0x02
#define DMA_ADDR_2		0x04
#define DMA_ADDR_3		0x06
#define DMA_ADDR_4		0xC0
#define DMA_ADDR_5		0xC4
#define DMA_ADDR_6		0xC8
#define DMA_ADDR_7		0xCC

#define DMA_CNT_0		0x01	/* DMA count registers */
#define DMA_CNT_1		0x03
#define DMA_CNT_2		0x05
#define DMA_CNT_3		0x07
#define DMA_CNT_4		0xC2
#define DMA_CNT_5		0xC6
#define DMA_CNT_6		0xCA
#define DMA_CNT_7		0xCE

#define DMA_LO_PAGE_0		0x87	/* DMA page registers */
#define DMA_LO_PAGE_1		0x83
#define DMA_LO_PAGE_2		0x81
#define DMA_LO_PAGE_3		0x82
#define DMA_LO_PAGE_5		0x8B
#define DMA_LO_PAGE_6		0x89
#define DMA_LO_PAGE_7		0x8A

#define DMA_HI_PAGE_0		0x487	/* DMA page registers */
#define DMA_HI_PAGE_1		0x483
#define DMA_HI_PAGE_2		0x481
#define DMA_HI_PAGE_3		0x482
#define DMA_HI_PAGE_5		0x48B
#define DMA_HI_PAGE_6		0x489
#define DMA_HI_PAGE_7		0x48A

#define DMA1_EXT_REG		0x40B
#define DMA2_EXT_REG		0x4D6

#ifndef __powerpc64__
    /* in arch/ppc/kernel/setup.c -- Cort */
    extern unsigned int DMA_MODE_WRITE;
    extern unsigned int DMA_MODE_READ;
    extern unsigned long ISA_DMA_THRESHOLD;
#else
    #define DMA_MODE_READ	0x44	/* I/O to memory, no autoinit, increment, single mode */
    #define DMA_MODE_WRITE	0x48	/* memory to I/O, no autoinit, increment, single mode */
#endif

#define DMA_MODE_CASCADE	0xC0	/* pass thru DREQ->HRQ, DACK<-HLDA only */

#define DMA_AUTOINIT		0x10

extern spinlock_t dma_spin_lock;

static __inline__ unsigned long claim_dma_lock(void)
{
	unsigned long flags;
	spin_lock_irqsave(&dma_spin_lock, flags);
	return flags;
}

static __inline__ void release_dma_lock(unsigned long flags)
{
	spin_unlock_irqrestore(&dma_spin_lock, flags);
}

/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
	unsigned char ucDmaCmd = 0x00;

if (dmanr != 4) {
		dma_outb(0, DMA2_MASK_REG);	/* This may not be enabled */
		dma_outb(ucDmaCmd, DMA2_CMD_REG);	/* Enable group */
	}
	if (dmanr <= 3) {
		dma_outb(dmanr, DMA1_MASK_REG);
		dma_outb(ucDmaCmd, DMA1_CMD_REG);	/* Enable group */
	} else {
		dma_outb(dmanr & 3, DMA2_MASK_REG);
	}
}

static __inline__ void disable_dma(unsigned int dmanr)
{
	if (dmanr <= 3)
		dma_outb(dmanr | 4, DMA1_MASK_REG);
	else
		dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
}

/* Clear the 'DMA Pointer Flip Flop'.
 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 * Use this once to initialize the FF to a known state.
 * After that, keep track of it. :-)
 * --- In order to do that, the DMA routines below should ---
 * --- only be used while interrupts are disabled! ---
 */
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
	if (dmanr <= 3)
		dma_outb(0, DMA1_CLEAR_FF_REG);
	else
		dma_outb(0, DMA2_CLEAR_FF_REG);
}

/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
	if (dmanr <= 3)
		dma_outb(mode | dmanr, DMA1_MODE_REG);
	else
		dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
}

/* Set only the page register bits of the transfer address.
 * This is used for successive transfers when we know the contents of
 * the lower 16 bits of the DMA current address register, but a 64k boundary
 * may have been crossed.
 */
static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
{
	switch (dmanr) {
	case 0:
		dma_outb(pagenr, DMA_LO_PAGE_0);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
		break;
	case 1:
		dma_outb(pagenr, DMA_LO_PAGE_1);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
		break;
	case 2:
		dma_outb(pagenr, DMA_LO_PAGE_2);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
		break;
	case 3:
		dma_outb(pagenr, DMA_LO_PAGE_3);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
		break;
	case 5:
		dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
		break;
	case 6:
		dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
		break;
	case 7:
		dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
		dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
		break;
	}
}

/* Set transfer address & page bits for specific DMA channel.
 * Assumes dma flipflop is clear.
 */
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
{
	if (dmanr <= 3) {
		dma_outb(phys & 0xff,
			 ((dmanr & 3) << 1) + IO_DMA1_BASE);
		dma_outb((phys >> 8) & 0xff,
			 ((dmanr & 3) << 1) + IO_DMA1_BASE);
	} else {
		dma_outb((phys >> 1) & 0xff,
			 ((dmanr & 3) << 2) + IO_DMA2_BASE);
		dma_outb((phys >> 9) & 0xff,
			 ((dmanr & 3) << 2) + IO_DMA2_BASE);
	}
	set_dma_page(dmanr, phys >> 16);
}

/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 * a specific DMA channel.
 * You must ensure the parameters are valid.
 * NOTE: from a manual: "the number of transfers is one more
 * than the initial word count"! This is taken into account.
 * Assumes dma flip-flop is clear.
 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 */
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
	count--;
	if (dmanr <= 3) {
		dma_outb(count & 0xff,
			 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
		dma_outb((count >> 8) & 0xff,
			 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
	} else {
		dma_outb((count >> 1) & 0xff,
			 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
		dma_outb((count >> 9) & 0xff,
			 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
	}
}

/* Get DMA residue count. After a DMA transfer, this
 * should return zero. Reading this while a DMA transfer is
 * still in progress will return unpredictable results.
 * If called before the channel has been used, it may return 1.
 * Otherwise, it returns the number of _bytes_ left to transfer.
 *
 * Assumes DMA flip-flop is clear.
 */
static __inline__ int get_dma_residue(unsigned int dmanr)
{
	unsigned int io_port = (dmanr <= 3)
	    ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
	    : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;

/* using short to get 16-bit wrap around */
	unsigned short count;

count = 1 + dma_inb(io_port);
	count += dma_inb(io_port) << 8;

return (dmanr <= 3) ? count : (count << 1);
}

/* These are in kernel/dma.c: */

/* reserve a DMA channel */
extern int request_dma(unsigned int dmanr, const char *device_id);
/* release it again */
extern void free_dma(unsigned int dmanr);

#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy	(0)
#endif

#endif /* __KERNEL__ */
#endif	/* _ASM_POWERPC_DMA_H */