OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	610 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 agp.h	596 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmregs.h	3.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 assembly.h	12.94 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 atomic.h	8.24 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 barrier.h	2.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	5.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	340 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	4.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 checksum.h	5.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compat.h	6.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat_ucontext.h	591 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	533 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	2.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	5.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dwarf.h	602 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 eisa_bus.h	702 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 eisa_eeprom.h	4.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	14.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	403 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	6.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	379 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 grfioctl.h	4.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	1.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardware.h	4.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hash.h	5.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	1.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	8.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kbdleds.h	477 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	221 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ldcw.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 led.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	759 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 machdep.h	349 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mckinley.h	270 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	195 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	527 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	5.42 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 parisc-device.h	1.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 parport.h	358 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	6.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pdc.h	3.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pdc_chassis.h	15.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pdcpat.h	15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	152 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	4.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	18.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 prefetch.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	9.86 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 psw.h	2.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	803 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 ropes.h	9.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rt_sigframe.h	745 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 runway.h	320 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	283 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	124 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	263 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	841 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	1.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 socket.h	311 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 special_insns.h	1015 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	4.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 spinlock_types.h	483 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	247 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 superio.h	3.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	332 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	1.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 termios.h	1.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	3.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	372 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlb.h	672 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	2.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	900 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	468 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	6.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucontext.h	327 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	472 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	5.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unwind.h	2.56 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: pci.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_PARISC_PCI_H
#define __ASM_PARISC_PCI_H

#include <linux/scatterlist.h>

/*
** HP PCI platforms generally support multiple bus adapters.
**    (workstations 1-~4, servers 2-~32)
**
** Newer platforms number the busses across PCI bus adapters *sparsely*.
** E.g. 0, 8, 16, ...
**
** Under a PCI bus, most HP platforms support PPBs up to two or three
** levels deep. See "Bit3" product line. 
*/
#define PCI_MAX_BUSSES	256

/* To be used as: mdelay(pci_post_reset_delay);
 *
 * post_reset is the time the kernel should stall to prevent anyone from
 * accessing the PCI bus once #RESET is de-asserted. 
 * PCI spec somewhere says 1 second but with multi-PCI bus systems,
 * this makes the boot time much longer than necessary.
 * 20ms seems to work for all the HP PCI implementations to date.
 */
#define pci_post_reset_delay 50

/*
** pci_hba_data (aka H2P_OBJECT in HP/UX)
**
** This is the "common" or "base" data structure which HBA drivers
** (eg Dino or LBA) are required to place at the top of their own
** platform_data structure.  I've heard this called "C inheritance" too.
**
** Data needed by pcibios layer belongs here.
*/
struct pci_hba_data {
	void __iomem   *base_addr;	/* aka Host Physical Address */
	const struct parisc_device *dev; /* device from PA bus walk */
	struct pci_bus *hba_bus;	/* primary PCI bus below HBA */
	int		hba_num;	/* I/O port space access "key" */
	struct resource bus_num;	/* PCI bus numbers */
	struct resource io_space;	/* PIOP */
	struct resource lmmio_space;	/* bus addresses < 4Gb */
	struct resource elmmio_space;	/* additional bus addresses < 4Gb */
	struct resource gmmio_space;	/* bus addresses > 4Gb */

/* NOTE: Dino code assumes it can use *all* of the lmmio_space,
	 * elmmio_space and gmmio_space as a contiguous array of
	 * resources.  This #define represents the array size */
	#define DINO_MAX_LMMIO_RESOURCES	3

unsigned long   lmmio_space_offset;  /* CPU view - PCI view */
	void *          iommu;          /* IOMMU this device is under */
	/* REVISIT - spinlock to protect resources? */

#define HBA_NAME_SIZE 16
	char io_name[HBA_NAME_SIZE];
	char lmmio_name[HBA_NAME_SIZE];
	char elmmio_name[HBA_NAME_SIZE];
	char gmmio_name[HBA_NAME_SIZE];
};

#define HBA_DATA(d)		((struct pci_hba_data *) (d))

/* 
** We support 2^16 I/O ports per HBA.  These are set up in the form
** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
** space address.
*/
#define HBA_PORT_SPACE_BITS	16

#define HBA_PORT_BASE(h)	((h) << HBA_PORT_SPACE_BITS)
#define HBA_PORT_SPACE_SIZE	(1UL << HBA_PORT_SPACE_BITS)

#define PCI_PORT_HBA(a)		((a) >> HBA_PORT_SPACE_BITS)
#define PCI_PORT_ADDR(a)	((a) & (HBA_PORT_SPACE_SIZE - 1))

#ifdef CONFIG_64BIT
#define PCI_F_EXTEND		0xffffffff00000000UL
#else	/* !CONFIG_64BIT */
#define PCI_F_EXTEND		0UL
#endif /* !CONFIG_64BIT */

/*
 * If the PCI device's view of memory is the same as the CPU's view of memory,
 * PCI_DMA_BUS_IS_PHYS is true.  The networking and block device layers use
 * this boolean for bounce buffer decisions.
 */
#ifdef CONFIG_PA20
/* All PA-2.0 machines have an IOMMU. */
#define PCI_DMA_BUS_IS_PHYS	0
#define parisc_has_iommu()	do { } while (0)
#else

#if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA)
extern int parisc_bus_is_phys; 	/* in arch/parisc/kernel/setup.c */
#define PCI_DMA_BUS_IS_PHYS	parisc_bus_is_phys
#define parisc_has_iommu()	do { parisc_bus_is_phys = 0; } while (0)
#else
#define PCI_DMA_BUS_IS_PHYS	1
#define parisc_has_iommu()	do { } while (0)
#endif

#endif	/* !CONFIG_PA20 */

/*
** Most PCI devices (eg Tulip, NCR720) also export the same registers
** to both MMIO and I/O port space.  Due to poor performance of I/O Port
** access under HP PCI bus adapters, strongly recommend the use of MMIO
** address space.
**
** While I'm at it more PA programming notes:
**
** 1) MMIO stores (writes) are posted operations. This means the processor
**    gets an "ACK" before the write actually gets to the device. A read
**    to the same device (or typically the bus adapter above it) will
**    force in-flight write transaction(s) out to the targeted device
**    before the read can complete.
**
** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
**    respect to DMA on all platforms. Ie PIO data can reach the processor
**    before in-flight DMA reaches memory. Since most SMP PA platforms
**    are I/O coherent, it generally doesn't matter...but sometimes
**    it does.
**
** I've helped device driver writers debug both types of problems.
*/
struct pci_port_ops {
	  u8 (*inb)  (struct pci_hba_data *hba, u16 port);
	 u16 (*inw)  (struct pci_hba_data *hba, u16 port);
	 u32 (*inl)  (struct pci_hba_data *hba, u16 port);
	void (*outb) (struct pci_hba_data *hba, u16 port,  u8 data);
	void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
	void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
};

struct pci_bios_ops {
	void (*init)(void);
	void (*fixup_bus)(struct pci_bus *bus);
};

/*
** Stuff declared in arch/parisc/kernel/pci.c
*/
extern struct pci_port_ops *pci_port;
extern struct pci_bios_ops *pci_bios;

#ifdef CONFIG_PCI
extern void pcibios_register_hba(struct pci_hba_data *);
#else
static inline void pcibios_register_hba(struct pci_hba_data *x)
{
}
#endif
extern void pcibios_init_bridge(struct pci_dev *);

/*
 * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
 *   0 == check if bridge is numbered before re-numbering.
 *   1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
 *
 *   We *should* set this to zero for "legacy" platforms and one
 *   for PAT platforms.
 *
 *   But legacy platforms also need to renumber the busses below a Host
 *   Bus controller.  Adding a 4-port Tulip card on the first PCI root
 *   bus of a C200 resulted in the secondary bus being numbered as 1.
 *   The second PCI host bus controller's root bus had already been
 *   assigned bus number 1 by firmware and sysfs complained.
 *
 *   Firmware isn't doing anything wrong here since each controller
 *   is its own PCI domain.  It's simpler and easier for us to renumber
 *   the busses rather than treat each Dino as a separate PCI domain.
 *   Eventually, we may want to introduce PCI domains for Superdome or
 *   rp7420/8420 boxes and then revisit this issue.
 */
#define pcibios_assign_all_busses()     (1)

#define PCIBIOS_MIN_IO          0x10
#define PCIBIOS_MIN_MEM         0x1000 /* NBPG - but pci/setup-res.c dies */

static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
{
	return channel ? 15 : 14;
}

#define HAVE_PCI_MMAP
#define ARCH_GENERIC_PCI_MMAP_RESOURCE

#endif /* __ASM_PARISC_PCI_H */