OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	610 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 agp.h	596 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmregs.h	3.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 assembly.h	12.94 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 atomic.h	8.24 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 barrier.h	2.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	5.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	340 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	4.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 checksum.h	5.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compat.h	6.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat_ucontext.h	591 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	533 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	2.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	5.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dwarf.h	602 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 eisa_bus.h	702 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 eisa_eeprom.h	4.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	14.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	403 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	6.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	379 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 grfioctl.h	4.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	1.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardware.h	4.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hash.h	5.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	1.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	8.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kbdleds.h	477 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	221 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ldcw.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 led.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	759 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 machdep.h	349 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mckinley.h	270 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	195 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	527 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	5.42 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 parisc-device.h	1.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 parport.h	358 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	6.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pdc.h	3.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pdc_chassis.h	15.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pdcpat.h	15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	152 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	4.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	18.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 prefetch.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	9.86 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 psw.h	2.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	803 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 ropes.h	9.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rt_sigframe.h	745 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 runway.h	320 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	283 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	124 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	263 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	841 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	1.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 socket.h	311 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 special_insns.h	1015 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	4.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 spinlock_types.h	483 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	247 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 superio.h	3.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	332 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	1.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 termios.h	1.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	3.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	372 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlb.h	672 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	2.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	900 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	468 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	6.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucontext.h	327 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	472 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	5.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unwind.h	2.56 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: atomic.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
 * Copyright (C) 2006 Kyle McMartin <kyle@parisc-linux.org>
 */

#ifndef _ASM_PARISC_ATOMIC_H_
#define _ASM_PARISC_ATOMIC_H_

#include <linux/types.h>
#include <asm/cmpxchg.h>
#include <asm/barrier.h>

/*
 * Atomic operations that C can't guarantee us.  Useful for
 * resource counting etc..
 *
 * And probably incredibly slow on parisc.  OTOH, we don't
 * have to write any serious assembly.   prumpf
 */

#ifdef CONFIG_SMP
#include <asm/spinlock.h>
#include <asm/cache.h>		/* we use L1_CACHE_BYTES */

/* Use an array of spinlocks for our atomic_ts.
 * Hash function to index into a different SPINLOCK.
 * Since "a" is usually an address, use one spinlock per cacheline.
 */
#  define ATOMIC_HASH_SIZE 4
#  define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) (a))/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ]))

extern arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned;

/* Can't use raw_spin_lock_irq because of #include problems, so
 * this is the substitute */
#define _atomic_spin_lock_irqsave(l,f) do {	\
	arch_spinlock_t *s = ATOMIC_HASH(l);		\
	local_irq_save(f);			\
	arch_spin_lock(s);			\
} while(0)

#define _atomic_spin_unlock_irqrestore(l,f) do {	\
	arch_spinlock_t *s = ATOMIC_HASH(l);			\
	arch_spin_unlock(s);				\
	local_irq_restore(f);				\
} while(0)

#else
#  define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0)
#  define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0)
#endif

/*
 * Note that we need not lock read accesses - aligned word writes/reads
 * are atomic, so a reader never sees inconsistent values.
 */

static __inline__ void atomic_set(atomic_t *v, int i)
{
	unsigned long flags;
	_atomic_spin_lock_irqsave(v, flags);

v->counter = i;

_atomic_spin_unlock_irqrestore(v, flags);
}

#define atomic_set_release(v, i)	atomic_set((v), (i))

static __inline__ int atomic_read(const atomic_t *v)
{
	return READ_ONCE((v)->counter);
}

/* exported interface */
#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))

/**
 * __atomic_add_unless - add unless the number is a given value
 * @v: pointer of type atomic_t
 * @a: the amount to add to v...
 * @u: ...unless v is equal to u.
 *
 * Atomically adds @a to @v, so long as it was not @u.
 * Returns the old value of @v.
 */
static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
{
	int c, old;
	c = atomic_read(v);
	for (;;) {
		if (unlikely(c == (u)))
			break;
		old = atomic_cmpxchg((v), c, c + (a));
		if (likely(old == c))
			break;
		c = old;
	}
	return c;
}

#define ATOMIC_OP(op, c_op)						\
static __inline__ void atomic_##op(int i, atomic_t *v)			\
{									\
	unsigned long flags;						\
									\
	_atomic_spin_lock_irqsave(v, flags);				\
	v->counter c_op i;						\
	_atomic_spin_unlock_irqrestore(v, flags);			\
}									\

#define ATOMIC_OP_RETURN(op, c_op)					\
static __inline__ int atomic_##op##_return(int i, atomic_t *v)		\
{									\
	unsigned long flags;						\
	int ret;							\
									\
	_atomic_spin_lock_irqsave(v, flags);				\
	ret = (v->counter c_op i);					\
	_atomic_spin_unlock_irqrestore(v, flags);			\
									\
	return ret;							\
}

#define ATOMIC_FETCH_OP(op, c_op)					\
static __inline__ int atomic_fetch_##op(int i, atomic_t *v)		\
{									\
	unsigned long flags;						\
	int ret;							\
									\
	_atomic_spin_lock_irqsave(v, flags);				\
	ret = v->counter;						\
	v->counter c_op i;						\
	_atomic_spin_unlock_irqrestore(v, flags);			\
									\
	return ret;							\
}

#define ATOMIC_OPS(op, c_op)						\
	ATOMIC_OP(op, c_op)						\
	ATOMIC_OP_RETURN(op, c_op)					\
	ATOMIC_FETCH_OP(op, c_op)

ATOMIC_OPS(add, +=)
ATOMIC_OPS(sub, -=)

#undef ATOMIC_OPS
#define ATOMIC_OPS(op, c_op)						\
	ATOMIC_OP(op, c_op)						\
	ATOMIC_FETCH_OP(op, c_op)

ATOMIC_OPS(and, &=)
ATOMIC_OPS(or, |=)
ATOMIC_OPS(xor, ^=)

#undef ATOMIC_OPS
#undef ATOMIC_FETCH_OP
#undef ATOMIC_OP_RETURN
#undef ATOMIC_OP

#define atomic_inc(v)	(atomic_add(   1,(v)))
#define atomic_dec(v)	(atomic_add(  -1,(v)))

#define atomic_inc_return(v)	(atomic_add_return(   1,(v)))
#define atomic_dec_return(v)	(atomic_add_return(  -1,(v)))

#define atomic_add_negative(a, v)	(atomic_add_return((a), (v)) < 0)

/*
 * atomic_inc_and_test - increment and test
 * @v: pointer of type atomic_t
 *
 * Atomically increments @v by 1
 * and returns true if the result is zero, or false for all
 * other cases.
 */
#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)

#define atomic_dec_and_test(v)	(atomic_dec_return(v) == 0)

#define atomic_sub_and_test(i,v)	(atomic_sub_return((i),(v)) == 0)

#define ATOMIC_INIT(i)	{ (i) }

#ifdef CONFIG_64BIT

#define ATOMIC64_INIT(i) { (i) }

#define ATOMIC64_OP(op, c_op)						\
static __inline__ void atomic64_##op(s64 i, atomic64_t *v)		\
{									\
	unsigned long flags;						\
									\
	_atomic_spin_lock_irqsave(v, flags);				\
	v->counter c_op i;						\
	_atomic_spin_unlock_irqrestore(v, flags);			\
}									\

#define ATOMIC64_OP_RETURN(op, c_op)					\
static __inline__ s64 atomic64_##op##_return(s64 i, atomic64_t *v)	\
{									\
	unsigned long flags;						\
	s64 ret;							\
									\
	_atomic_spin_lock_irqsave(v, flags);				\
	ret = (v->counter c_op i);					\
	_atomic_spin_unlock_irqrestore(v, flags);			\
									\
	return ret;							\
}

#define ATOMIC64_FETCH_OP(op, c_op)					\
static __inline__ s64 atomic64_fetch_##op(s64 i, atomic64_t *v)		\
{									\
	unsigned long flags;						\
	s64 ret;							\
									\
	_atomic_spin_lock_irqsave(v, flags);				\
	ret = v->counter;						\
	v->counter c_op i;						\
	_atomic_spin_unlock_irqrestore(v, flags);			\
									\
	return ret;							\
}

#define ATOMIC64_OPS(op, c_op)						\
	ATOMIC64_OP(op, c_op)						\
	ATOMIC64_OP_RETURN(op, c_op)					\
	ATOMIC64_FETCH_OP(op, c_op)

ATOMIC64_OPS(add, +=)
ATOMIC64_OPS(sub, -=)

#undef ATOMIC64_OPS
#define ATOMIC64_OPS(op, c_op)						\
	ATOMIC64_OP(op, c_op)						\
	ATOMIC64_FETCH_OP(op, c_op)

ATOMIC64_OPS(and, &=)
ATOMIC64_OPS(or, |=)
ATOMIC64_OPS(xor, ^=)

#undef ATOMIC64_OPS
#undef ATOMIC64_FETCH_OP
#undef ATOMIC64_OP_RETURN
#undef ATOMIC64_OP

static __inline__ void
atomic64_set(atomic64_t *v, s64 i)
{
	unsigned long flags;
	_atomic_spin_lock_irqsave(v, flags);

v->counter = i;

_atomic_spin_unlock_irqrestore(v, flags);
}

#define atomic64_set_release(v, i)	atomic64_set((v), (i))

static __inline__ s64
atomic64_read(const atomic64_t *v)
{
	return READ_ONCE((v)->counter);
}

#define atomic64_inc(v)		(atomic64_add(   1,(v)))
#define atomic64_dec(v)		(atomic64_add(  -1,(v)))

#define atomic64_inc_return(v)		(atomic64_add_return(   1,(v)))
#define atomic64_dec_return(v)		(atomic64_add_return(  -1,(v)))

#define atomic64_add_negative(a, v)	(atomic64_add_return((a), (v)) < 0)

#define atomic64_inc_and_test(v) 	(atomic64_inc_return(v) == 0)
#define atomic64_dec_and_test(v)	(atomic64_dec_return(v) == 0)
#define atomic64_sub_and_test(i,v)	(atomic64_sub_return((i),(v)) == 0)

/* exported interface */
#define atomic64_cmpxchg(v, o, n) \
	((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))

/**
 * atomic64_add_unless - add unless the number is a given value
 * @v: pointer of type atomic64_t
 * @a: the amount to add to v...
 * @u: ...unless v is equal to u.
 *
 * Atomically adds @a to @v, so long as it was not @u.
 * Returns the old value of @v.
 */
static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
{
	long c, old;
	c = atomic64_read(v);
	for (;;) {
		if (unlikely(c == (u)))
			break;
		old = atomic64_cmpxchg((v), c, c + (a));
		if (likely(old == c))
			break;
		c = old;
	}
	return c != (u);
}

#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)

/*
 * atomic64_dec_if_positive - decrement by 1 if old value positive
 * @v: pointer of type atomic_t
 *
 * The function returns the old value of *v minus 1, even if
 * the atomic variable, v, was not decremented.
 */
static inline long atomic64_dec_if_positive(atomic64_t *v)
{
	long c, old, dec;
	c = atomic64_read(v);
	for (;;) {
		dec = c - 1;
		if (unlikely(dec < 0))
			break;
		old = atomic64_cmpxchg((v), c, dec);
		if (likely(old == c))
			break;
		c = old;
	}
	return dec;
}

#endif /* !CONFIG_64BIT */

#endif /* _ASM_PARISC_ATOMIC_H_ */