OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	314 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	4.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	5.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	864 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	561 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 busctl-regs.h	7.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	2.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	7.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	2.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu-regs.h	16.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	922 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 debugger.h	1.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	597 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 div64.h	3.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	636 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	3.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dmactl-regs.h	532 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	4.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emergency-restart.h	43 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 exceptions.h	4.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu.h	3.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 frame.inc	2.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 futex.h	31 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 gdb-stub.h	5.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	3.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	483 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 intctl-regs.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	7.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_regs.h	751 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	4.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	561 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	1.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	160 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	593 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 local.h	31 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 local64.h	33 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	26 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	434 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	4.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 page_offset.h	302 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	2.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 pgtable.h	15.68 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pio-regs.h	7.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	4.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	805 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 reset-regs.h	1.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rtc-regs.h	3.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 rwlock.h	2.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial-regs.h	8.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	574 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	182 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	888 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	3.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smsc911x.h	27 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	3.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	445 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	2.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 termios.h	387 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	4.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timer-regs.h	20.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	843 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	941 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	34 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	620 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	7.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucontext.h	673 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	678 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	471 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 xor.h	29 bytes	01/28/2018 09:20:33 PM	rw-r--r--

Editing: cacheflush.h

/* MN10300 Cache flushing
 *
 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public Licence
 * as published by the Free Software Foundation; either version
 * 2 of the Licence, or (at your option) any later version.
 */
#ifndef _ASM_CACHEFLUSH_H
#define _ASM_CACHEFLUSH_H

#ifndef __ASSEMBLY__

/* Keep includes the same across arches.  */
#include <linux/mm.h>

/*
 * Primitive routines
 */
#ifdef CONFIG_MN10300_CACHE_ENABLED
extern void mn10300_local_icache_inv(void);
extern void mn10300_local_icache_inv_page(unsigned long start);
extern void mn10300_local_icache_inv_range(unsigned long start, unsigned long end);
extern void mn10300_local_icache_inv_range2(unsigned long start, unsigned long size);
extern void mn10300_local_dcache_inv(void);
extern void mn10300_local_dcache_inv_page(unsigned long start);
extern void mn10300_local_dcache_inv_range(unsigned long start, unsigned long end);
extern void mn10300_local_dcache_inv_range2(unsigned long start, unsigned long size);
extern void mn10300_icache_inv(void);
extern void mn10300_icache_inv_page(unsigned long start);
extern void mn10300_icache_inv_range(unsigned long start, unsigned long end);
extern void mn10300_icache_inv_range2(unsigned long start, unsigned long size);
extern void mn10300_dcache_inv(void);
extern void mn10300_dcache_inv_page(unsigned long start);
extern void mn10300_dcache_inv_range(unsigned long start, unsigned long end);
extern void mn10300_dcache_inv_range2(unsigned long start, unsigned long size);
#ifdef CONFIG_MN10300_CACHE_WBACK
extern void mn10300_local_dcache_flush(void);
extern void mn10300_local_dcache_flush_page(unsigned long start);
extern void mn10300_local_dcache_flush_range(unsigned long start, unsigned long end);
extern void mn10300_local_dcache_flush_range2(unsigned long start, unsigned long size);
extern void mn10300_local_dcache_flush_inv(void);
extern void mn10300_local_dcache_flush_inv_page(unsigned long start);
extern void mn10300_local_dcache_flush_inv_range(unsigned long start, unsigned long end);
extern void mn10300_local_dcache_flush_inv_range2(unsigned long start, unsigned long size);
extern void mn10300_dcache_flush(void);
extern void mn10300_dcache_flush_page(unsigned long start);
extern void mn10300_dcache_flush_range(unsigned long start, unsigned long end);
extern void mn10300_dcache_flush_range2(unsigned long start, unsigned long size);
extern void mn10300_dcache_flush_inv(void);
extern void mn10300_dcache_flush_inv_page(unsigned long start);
extern void mn10300_dcache_flush_inv_range(unsigned long start, unsigned long end);
extern void mn10300_dcache_flush_inv_range2(unsigned long start, unsigned long size);
#else
#define mn10300_local_dcache_flush()			do {} while (0)
#define mn10300_local_dcache_flush_page(start)		do {} while (0)
#define mn10300_local_dcache_flush_range(start, end)	do {} while (0)
#define mn10300_local_dcache_flush_range2(start, size)	do {} while (0)
#define mn10300_local_dcache_flush_inv() \
		mn10300_local_dcache_inv()
#define mn10300_local_dcache_flush_inv_page(start) \
		mn10300_local_dcache_inv_page(start)
#define mn10300_local_dcache_flush_inv_range(start, end) \
		mn10300_local_dcache_inv_range(start, end)
#define mn10300_local_dcache_flush_inv_range2(start, size) \
		mn10300_local_dcache_inv_range2(start, size)
#define mn10300_dcache_flush()				do {} while (0)
#define mn10300_dcache_flush_page(start)		do {} while (0)
#define mn10300_dcache_flush_range(start, end)		do {} while (0)
#define mn10300_dcache_flush_range2(start, size)	do {} while (0)
#define mn10300_dcache_flush_inv()			mn10300_dcache_inv()
#define mn10300_dcache_flush_inv_page(start) \
	mn10300_dcache_inv_page((start))
#define mn10300_dcache_flush_inv_range(start, end) \
	mn10300_dcache_inv_range((start), (end))
#define mn10300_dcache_flush_inv_range2(start, size) \
	mn10300_dcache_inv_range2((start), (size))
#endif /* CONFIG_MN10300_CACHE_WBACK */
#else
#define mn10300_local_icache_inv()			do {} while (0)
#define mn10300_local_icache_inv_page(start)		do {} while (0)
#define mn10300_local_icache_inv_range(start, end)	do {} while (0)
#define mn10300_local_icache_inv_range2(start, size)	do {} while (0)
#define mn10300_local_dcache_inv()			do {} while (0)
#define mn10300_local_dcache_inv_page(start)		do {} while (0)
#define mn10300_local_dcache_inv_range(start, end)	do {} while (0)
#define mn10300_local_dcache_inv_range2(start, size)	do {} while (0)
#define mn10300_local_dcache_flush()			do {} while (0)
#define mn10300_local_dcache_flush_inv_page(start)	do {} while (0)
#define mn10300_local_dcache_flush_inv()		do {} while (0)
#define mn10300_local_dcache_flush_inv_range(start, end)do {} while (0)
#define mn10300_local_dcache_flush_inv_range2(start, size) do {} while (0)
#define mn10300_local_dcache_flush_page(start)		do {} while (0)
#define mn10300_local_dcache_flush_range(start, end)	do {} while (0)
#define mn10300_local_dcache_flush_range2(start, size)	do {} while (0)
#define mn10300_icache_inv()				do {} while (0)
#define mn10300_icache_inv_page(start)			do {} while (0)
#define mn10300_icache_inv_range(start, end)		do {} while (0)
#define mn10300_icache_inv_range2(start, size)		do {} while (0)
#define mn10300_dcache_inv()				do {} while (0)
#define mn10300_dcache_inv_page(start)			do {} while (0)
#define mn10300_dcache_inv_range(start, end)		do {} while (0)
#define mn10300_dcache_inv_range2(start, size)		do {} while (0)
#define mn10300_dcache_flush()				do {} while (0)
#define mn10300_dcache_flush_inv_page(start)		do {} while (0)
#define mn10300_dcache_flush_inv()			do {} while (0)
#define mn10300_dcache_flush_inv_range(start, end)	do {} while (0)
#define mn10300_dcache_flush_inv_range2(start, size)	do {} while (0)
#define mn10300_dcache_flush_page(start)		do {} while (0)
#define mn10300_dcache_flush_range(start, end)		do {} while (0)
#define mn10300_dcache_flush_range2(start, size)	do {} while (0)
#endif /* CONFIG_MN10300_CACHE_ENABLED */

/*
 * Virtually-indexed cache management (our cache is physically indexed)
 */
#define flush_cache_all()			do {} while (0)
#define flush_cache_mm(mm)			do {} while (0)
#define flush_cache_dup_mm(mm)			do {} while (0)
#define flush_cache_range(mm, start, end)	do {} while (0)
#define flush_cache_page(vma, vmaddr, pfn)	do {} while (0)
#define flush_cache_vmap(start, end)		do {} while (0)
#define flush_cache_vunmap(start, end)		do {} while (0)
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
#define flush_dcache_page(page)			do {} while (0)
#define flush_dcache_mmap_lock(mapping)		do {} while (0)
#define flush_dcache_mmap_unlock(mapping)	do {} while (0)

/*
 * Physically-indexed cache management
 */
#if defined(CONFIG_MN10300_CACHE_FLUSH_ICACHE)
extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
extern void flush_icache_range(unsigned long start, unsigned long end);
#elif defined(CONFIG_MN10300_CACHE_INV_ICACHE)
static inline void flush_icache_page(struct vm_area_struct *vma,
				     struct page *page)
{
	mn10300_icache_inv_page(page_to_phys(page));
}
extern void flush_icache_range(unsigned long start, unsigned long end);
#else
#define flush_icache_range(start, end)		do {} while (0)
#define flush_icache_page(vma, pg)		do {} while (0)
#endif

#define flush_icache_user_range(vma, pg, adr, len) \
	flush_icache_range(adr, adr + len)

#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
	do {					\
		memcpy(dst, src, len);		\
		flush_icache_page(vma, page);	\
	} while (0)

#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
	memcpy(dst, src, len)

#endif /* __ASSEMBLY__ */

#endif /* _ASM_CACHEFLUSH_H */