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..
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11/17/2022 06:42:15 AM
rwxr-xr-x
📄
Kbuild
568 bytes
01/28/2018 09:20:33 PM
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arch_gicv3.h
9.05 KB
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arch_timer.h
2.48 KB
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arm-cci.h
1.05 KB
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asm-offsets.h
35 bytes
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assembler.h
10.46 KB
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atomic.h
13.22 KB
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auxvec.h
29 bytes
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bL_switcher.h
2.28 KB
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barrier.h
2.84 KB
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bitops.h
8.62 KB
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bitrev.h
451 bytes
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bug.h
2.46 KB
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bugs.h
546 bytes
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cache.h
813 bytes
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cacheflush.h
15.54 KB
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cachetype.h
2.71 KB
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checksum.h
3.71 KB
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clocksource.h
153 bytes
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cmpxchg.h
6.14 KB
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compiler.h
978 bytes
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cp15.h
3.84 KB
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cpu.h
533 bytes
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cpufeature.h
1.4 KB
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cpuidle.h
1.33 KB
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cputype.h
8.42 KB
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cti.h
3.62 KB
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dcc.h
1.01 KB
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delay.h
2.83 KB
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device.h
771 bytes
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div64.h
3.17 KB
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dma-contiguous.h
265 bytes
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dma-iommu.h
1.01 KB
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dma-mapping.h
7.44 KB
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dma.h
4.18 KB
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dmi.h
528 bytes
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domain.h
3.65 KB
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ecard.h
5.98 KB
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edac.h
1.51 KB
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efi.h
3.04 KB
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elf.h
4.52 KB
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entry-macro-multi.S
726 bytes
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exception.h
571 bytes
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fb.h
375 bytes
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fiq.h
1.36 KB
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firmware.h
1.82 KB
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fixmap.h
1.84 KB
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flat.h
915 bytes
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floppy.h
3.61 KB
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fncpy.h
3.08 KB
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fpstate.h
1.73 KB
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ftrace.h
1.92 KB
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futex.h
4.24 KB
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glue-cache.h
3.51 KB
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glue-df.h
2.2 KB
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glue-pf.h
1.12 KB
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glue-proc.h
4.46 KB
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glue.h
759 bytes
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gpio.h
693 bytes
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hardirq.h
803 bytes
11/01/2022 04:52:05 PM
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hardware
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11/17/2022 06:42:18 AM
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highmem.h
2.15 KB
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hugetlb-3level.h
2.03 KB
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hugetlb.h
1.78 KB
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hw_breakpoint.h
3.53 KB
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hw_irq.h
349 bytes
01/28/2018 09:20:33 PM
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hwcap.h
378 bytes
01/28/2018 09:20:33 PM
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hypervisor.h
140 bytes
01/28/2018 09:20:33 PM
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ide.h
566 bytes
01/28/2018 09:20:33 PM
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idmap.h
355 bytes
01/28/2018 09:20:33 PM
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insn.h
636 bytes
11/01/2022 04:52:05 PM
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io.h
15.96 KB
01/28/2018 09:20:33 PM
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irq.h
1015 bytes
11/01/2022 04:52:05 PM
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irq_work.h
234 bytes
01/28/2018 09:20:33 PM
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irqflags.h
3.88 KB
01/28/2018 09:20:33 PM
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jump_label.h
1009 bytes
01/28/2018 09:20:33 PM
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📄
kexec-internal.h
272 bytes
11/01/2022 04:52:05 PM
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kexec.h
2.3 KB
01/28/2018 09:20:33 PM
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kgdb.h
2.72 KB
11/01/2022 04:52:05 PM
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kmap_types.h
190 bytes
01/28/2018 09:20:33 PM
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kprobes.h
2.65 KB
11/01/2022 04:52:05 PM
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kvm_arm.h
7.6 KB
01/28/2018 09:20:33 PM
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kvm_asm.h
2.84 KB
11/01/2022 04:52:05 PM
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kvm_coproc.h
1.99 KB
01/28/2018 09:20:33 PM
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kvm_emulate.h
7.84 KB
11/01/2022 04:52:05 PM
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kvm_host.h
10.31 KB
11/01/2022 04:52:05 PM
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kvm_hyp.h
4.49 KB
01/28/2018 09:20:33 PM
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kvm_mmio.h
1.34 KB
11/01/2022 04:52:05 PM
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kvm_mmu.h
7.27 KB
11/01/2022 04:52:05 PM
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📄
limits.h
166 bytes
01/28/2018 09:20:33 PM
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linkage.h
216 bytes
01/28/2018 09:20:33 PM
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📁
mach
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11/17/2022 06:42:18 AM
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mc146818rtc.h
720 bytes
01/28/2018 09:20:33 PM
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mcpm.h
11.92 KB
01/28/2018 09:20:33 PM
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mcs_spinlock.h
570 bytes
01/28/2018 09:20:33 PM
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memblock.h
248 bytes
01/28/2018 09:20:33 PM
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memory.h
10.12 KB
01/28/2018 09:20:33 PM
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mmu.h
953 bytes
01/28/2018 09:20:33 PM
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mmu_context.h
3.94 KB
01/28/2018 09:20:33 PM
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module.h
1.57 KB
11/01/2022 04:52:05 PM
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mpu.h
2.15 KB
01/28/2018 09:20:33 PM
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mtd-xip.h
666 bytes
01/28/2018 09:20:33 PM
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neon.h
1.16 KB
01/28/2018 09:20:33 PM
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nwflash.h
252 bytes
01/28/2018 09:20:33 PM
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opcodes-sec.h
742 bytes
01/28/2018 09:20:33 PM
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opcodes-virt.h
1.32 KB
01/28/2018 09:20:33 PM
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opcodes.h
8.07 KB
01/28/2018 09:20:33 PM
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outercache.h
3.78 KB
01/28/2018 09:20:33 PM
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page-nommu.h
957 bytes
01/28/2018 09:20:33 PM
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page.h
3.61 KB
01/28/2018 09:20:33 PM
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paravirt.h
454 bytes
01/28/2018 09:20:33 PM
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patch.h
438 bytes
01/28/2018 09:20:33 PM
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pci.h
956 bytes
01/28/2018 09:20:33 PM
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percpu.h
1.56 KB
11/01/2022 04:52:05 PM
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perf_event.h
850 bytes
01/28/2018 09:20:33 PM
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pgalloc.h
3.79 KB
01/28/2018 09:20:33 PM
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pgtable-2level-hwdef.h
3.45 KB
01/28/2018 09:20:33 PM
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pgtable-2level-types.h
1.84 KB
01/28/2018 09:20:33 PM
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pgtable-2level.h
8.51 KB
11/01/2022 04:52:05 PM
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pgtable-3level-hwdef.h
3.95 KB
01/28/2018 09:20:33 PM
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pgtable-3level-types.h
1.89 KB
01/28/2018 09:20:33 PM
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pgtable-3level.h
9.54 KB
11/01/2022 04:52:05 PM
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pgtable-hwdef.h
467 bytes
01/28/2018 09:20:33 PM
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pgtable-nommu.h
2.66 KB
01/28/2018 09:20:33 PM
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pgtable.h
11.68 KB
01/28/2018 09:20:33 PM
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probes.h
1.73 KB
01/28/2018 09:20:33 PM
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proc-fns.h
4.79 KB
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processor.h
3.4 KB
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procinfo.h
1.27 KB
01/28/2018 09:20:33 PM
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prom.h
715 bytes
01/28/2018 09:20:33 PM
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psci.h
771 bytes
01/28/2018 09:20:33 PM
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ptrace.h
4.89 KB
11/01/2022 04:52:05 PM
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sections.h
189 bytes
01/28/2018 09:20:33 PM
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set_memory.h
1.04 KB
01/28/2018 09:20:33 PM
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setup.h
934 bytes
01/28/2018 09:20:33 PM
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shmparam.h
419 bytes
01/28/2018 09:20:33 PM
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signal.h
500 bytes
01/28/2018 09:20:33 PM
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smp.h
3.1 KB
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smp_plat.h
2.48 KB
01/28/2018 09:20:33 PM
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smp_scu.h
1.32 KB
01/28/2018 09:20:33 PM
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smp_twd.h
908 bytes
01/28/2018 09:20:33 PM
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sparsemem.h
716 bytes
01/28/2018 09:20:33 PM
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spectre.h
906 bytes
11/01/2022 04:52:05 PM
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spinlock.h
5.49 KB
01/28/2018 09:20:33 PM
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spinlock_types.h
541 bytes
01/28/2018 09:20:33 PM
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stackprotector.h
1.09 KB
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stacktrace.h
742 bytes
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stage2_pgtable.h
2.12 KB
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string.h
1.43 KB
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suspend.h
369 bytes
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swab.h
1005 bytes
01/28/2018 09:20:33 PM
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switch_to.h
1.03 KB
01/28/2018 09:20:33 PM
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sync_bitops.h
1.03 KB
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syscall.h
2.48 KB
01/28/2018 09:20:33 PM
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system_info.h
763 bytes
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system_misc.h
1.14 KB
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tcm.h
937 bytes
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therm.h
655 bytes
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thread_info.h
5.2 KB
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thread_notify.h
1.2 KB
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timex.h
577 bytes
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tlb.h
7.37 KB
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tlbflush.h
17.88 KB
01/28/2018 09:20:33 PM
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tls.h
3.09 KB
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topology.h
1.18 KB
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traps.h
1.17 KB
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trusted_foundations.h
2.29 KB
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uaccess-asm.h
2.83 KB
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uaccess.h
16.22 KB
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ucontext.h
2.98 KB
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unaligned.h
846 bytes
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unified.h
1.61 KB
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unistd.h
1.68 KB
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unwind.h
1.71 KB
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uprobes.h
1.07 KB
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user.h
4.2 KB
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v7m.h
2.93 KB
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vdso.h
507 bytes
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vdso_datapage.h
1.69 KB
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vfp.h
2.86 KB
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vfpmacros.h
2.1 KB
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vga.h
305 bytes
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virt.h
2.9 KB
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word-at-a-time.h
2.08 KB
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xen
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xor.h
5.22 KB
01/28/2018 09:20:33 PM
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Editing: cti.h
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/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __ASMARM_CTI_H #define __ASMARM_CTI_H #include <asm/io.h> #include <asm/hardware/coresight.h> /* The registers' definition is from section 3.2 of * Embedded Cross Trigger Revision: r0p0 */ #define CTICONTROL 0x000 #define CTISTATUS 0x004 #define CTILOCK 0x008 #define CTIPROTECTION 0x00C #define CTIINTACK 0x010 #define CTIAPPSET 0x014 #define CTIAPPCLEAR 0x018 #define CTIAPPPULSE 0x01c #define CTIINEN 0x020 #define CTIOUTEN 0x0A0 #define CTITRIGINSTATUS 0x130 #define CTITRIGOUTSTATUS 0x134 #define CTICHINSTATUS 0x138 #define CTICHOUTSTATUS 0x13c #define CTIPERIPHID0 0xFE0 #define CTIPERIPHID1 0xFE4 #define CTIPERIPHID2 0xFE8 #define CTIPERIPHID3 0xFEC #define CTIPCELLID0 0xFF0 #define CTIPCELLID1 0xFF4 #define CTIPCELLID2 0xFF8 #define CTIPCELLID3 0xFFC /* The below are from section 3.6.4 of * CoreSight v1.0 Architecture Specification */ #define LOCKACCESS 0xFB0 #define LOCKSTATUS 0xFB4 /** * struct cti - cross trigger interface struct * @base: mapped virtual address for the cti base * @irq: irq number for the cti * @trig_out_for_irq: triger out number which will cause * the @irq happen * * cti struct used to operate cti registers. */ struct cti { void __iomem *base; int irq; int trig_out_for_irq; }; /** * cti_init - initialize the cti instance * @cti: cti instance * @base: mapped virtual address for the cti base * @irq: irq number for the cti * @trig_out: triger out number which will cause * the @irq happen * * called by machine code to pass the board dependent * @base, @irq and @trig_out to cti. */ static inline void cti_init(struct cti *cti, void __iomem *base, int irq, int trig_out) { cti->base = base; cti->irq = irq; cti->trig_out_for_irq = trig_out; } /** * cti_map_trigger - use the @chan to map @trig_in to @trig_out * @cti: cti instance * @trig_in: trigger in number * @trig_out: trigger out number * @channel: channel number * * This function maps one trigger in of @trig_in to one trigger * out of @trig_out using the channel @chan. */ static inline void cti_map_trigger(struct cti *cti, int trig_in, int trig_out, int chan) { void __iomem *base = cti->base; unsigned long val; val = __raw_readl(base + CTIINEN + trig_in * 4); val |= BIT(chan); __raw_writel(val, base + CTIINEN + trig_in * 4); val = __raw_readl(base + CTIOUTEN + trig_out * 4); val |= BIT(chan); __raw_writel(val, base + CTIOUTEN + trig_out * 4); } /** * cti_enable - enable the cti module * @cti: cti instance * * enable the cti module */ static inline void cti_enable(struct cti *cti) { __raw_writel(0x1, cti->base + CTICONTROL); } /** * cti_disable - disable the cti module * @cti: cti instance * * enable the cti module */ static inline void cti_disable(struct cti *cti) { __raw_writel(0, cti->base + CTICONTROL); } /** * cti_irq_ack - clear the cti irq * @cti: cti instance * * clear the cti irq */ static inline void cti_irq_ack(struct cti *cti) { void __iomem *base = cti->base; unsigned long val; val = __raw_readl(base + CTIINTACK); val |= BIT(cti->trig_out_for_irq); __raw_writel(val, base + CTIINTACK); } /** * cti_unlock - unlock cti module * @cti: cti instance * * unlock the cti module, or else any writes to the cti * module is not allowed. */ static inline void cti_unlock(struct cti *cti) { __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS); } /** * cti_lock - lock cti module * @cti: cti instance * * lock the cti module, so any writes to the cti * module will be not allowed. */ static inline void cti_lock(struct cti *cti) { __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS); } #endif