OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:15 AM	rwxr-xr-x
📄 Kbuild	568 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 arch_gicv3.h	9.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 arch_timer.h	2.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 arm-cci.h	1.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 assembler.h	10.46 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 atomic.h	13.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 auxvec.h	29 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bL_switcher.h	2.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	2.84 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	8.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitrev.h	451 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	2.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	546 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 cache.h	813 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	15.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cachetype.h	2.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	3.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocksource.h	153 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	6.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compiler.h	978 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cp15.h	3.84 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpu.h	533 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpufeature.h	1.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpuidle.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cputype.h	8.42 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cti.h	3.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcc.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	2.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	771 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 div64.h	3.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-contiguous.h	265 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-iommu.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	7.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	4.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dmi.h	528 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 domain.h	3.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ecard.h	5.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 edac.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 efi.h	3.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	4.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry-macro-multi.S	726 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 exception.h	571 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	375 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fiq.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 firmware.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	915 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	3.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fncpy.h	3.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpstate.h	1.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	1.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 futex.h	4.24 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 glue-cache.h	3.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 glue-df.h	2.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 glue-pf.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 glue-proc.h	4.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 glue.h	759 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 gpio.h	693 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	803 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📁 hardware	-	11/17/2022 06:42:18 AM	rwxr-xr-x
📄 highmem.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb-3level.h	2.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	1.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	3.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	349 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwcap.h	378 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hypervisor.h	140 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	566 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 idmap.h	355 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 insn.h	636 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 io.h	15.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1015 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 irq_work.h	234 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	3.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1009 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec-internal.h	272 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 kexec.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	2.72 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kmap_types.h	190 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	2.65 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_arm.h	7.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_asm.h	2.84 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_coproc.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_emulate.h	7.84 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_host.h	10.31 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_hyp.h	4.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_mmio.h	1.34 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_mmu.h	7.27 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 limits.h	166 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	216 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 mach	-	11/17/2022 06:42:18 AM	rwxr-xr-x
📄 mc146818rtc.h	720 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcpm.h	11.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mcs_spinlock.h	570 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 memblock.h	248 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 memory.h	10.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	953 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	3.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	1.57 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mpu.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mtd-xip.h	666 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 neon.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nwflash.h	252 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 opcodes-sec.h	742 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 opcodes-virt.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 opcodes.h	8.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 outercache.h	3.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page-nommu.h	957 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	3.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 paravirt.h	454 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 patch.h	438 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	956 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu.h	1.56 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 perf_event.h	850 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	3.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-2level-hwdef.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-2level-types.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-2level.h	8.51 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable-3level-hwdef.h	3.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-3level-types.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-3level.h	9.54 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable-hwdef.h	467 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-nommu.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	11.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 probes.h	1.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 proc-fns.h	4.79 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 processor.h	3.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 procinfo.h	1.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prom.h	715 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 psci.h	771 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	4.89 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sections.h	189 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 set_memory.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	934 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	419 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	500 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	3.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp_plat.h	2.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp_scu.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp_twd.h	908 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	716 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spectre.h	906 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 spinlock.h	5.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	541 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackprotector.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	742 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stage2_pgtable.h	2.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 suspend.h	369 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 swab.h	1005 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sync_bitops.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	2.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 system_info.h	763 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 system_misc.h	1.14 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tcm.h	937 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 therm.h	655 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	5.2 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 thread_notify.h	1.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	577 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlb.h	7.37 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlbflush.h	17.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tls.h	3.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 trusted_foundations.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess-asm.h	2.83 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 uaccess.h	16.22 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ucontext.h	2.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	846 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unified.h	1.61 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 unistd.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unwind.h	1.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uprobes.h	1.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	4.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 v7m.h	2.93 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 vdso.h	507 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 vdso_datapage.h	1.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vfp.h	2.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vfpmacros.h	2.1 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 vga.h	305 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 virt.h	2.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 word-at-a-time.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 xen	-	11/17/2022 06:42:18 AM	rwxr-xr-x
📄 xor.h	5.22 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: atomic.h

/*
 *  arch/arm/include/asm/atomic.h
 *
 *  Copyright (C) 1996 Russell King.
 *  Copyright (C) 2002 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __ASM_ARM_ATOMIC_H
#define __ASM_ARM_ATOMIC_H

#include <linux/compiler.h>
#include <linux/prefetch.h>
#include <linux/types.h>
#include <linux/irqflags.h>
#include <asm/barrier.h>
#include <asm/cmpxchg.h>

#define ATOMIC_INIT(i)	{ (i) }

#ifdef __KERNEL__

/*
 * On ARM, ordinary assignment (str instruction) doesn't clear the local
 * strex/ldrex monitor on some implementations. The reason we can use it for
 * atomic_set() is the clrex or dummy strex done on every exception return.
 */
#define atomic_read(v)	READ_ONCE((v)->counter)
#define atomic_set(v,i)	WRITE_ONCE(((v)->counter), (i))

#if __LINUX_ARM_ARCH__ >= 6

/*
 * ARMv6 UP and SMP safe atomic ops.  We use load exclusive and
 * store exclusive to ensure that these are atomic.  We may loop
 * to ensure that the update happens.
 */

#define ATOMIC_OP(op, c_op, asm_op)					\
static inline void atomic_##op(int i, atomic_t *v)			\
{									\
	unsigned long tmp;						\
	int result;							\
									\
	prefetchw(&v->counter);						\
	__asm__ __volatile__("@ atomic_" #op "\n"			\
"1:	ldrex	%0, [%3]\n"						\
"	" #asm_op "	%0, %0, %4\n"					\
"	strex	%1, %0, [%3]\n"						\
"	teq	%1, #0\n"						\
"	bne	1b"							\
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)		\
	: "r" (&v->counter), "Ir" (i)					\
	: "cc");							\
}									\

#define ATOMIC_OP_RETURN(op, c_op, asm_op)				\
static inline int atomic_##op##_return_relaxed(int i, atomic_t *v)	\
{									\
	unsigned long tmp;						\
	int result;							\
									\
	prefetchw(&v->counter);						\
									\
	__asm__ __volatile__("@ atomic_" #op "_return\n"		\
"1:	ldrex	%0, [%3]\n"						\
"	" #asm_op "	%0, %0, %4\n"					\
"	strex	%1, %0, [%3]\n"						\
"	teq	%1, #0\n"						\
"	bne	1b"							\
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)		\
	: "r" (&v->counter), "Ir" (i)					\
	: "cc");							\
									\
	return result;							\
}

#define ATOMIC_FETCH_OP(op, c_op, asm_op)				\
static inline int atomic_fetch_##op##_relaxed(int i, atomic_t *v)	\
{									\
	unsigned long tmp;						\
	int result, val;						\
									\
	prefetchw(&v->counter);						\
									\
	__asm__ __volatile__("@ atomic_fetch_" #op "\n"			\
"1:	ldrex	%0, [%4]\n"						\
"	" #asm_op "	%1, %0, %5\n"					\
"	strex	%2, %1, [%4]\n"						\
"	teq	%2, #0\n"						\
"	bne	1b"							\
	: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Qo" (v->counter)	\
	: "r" (&v->counter), "Ir" (i)					\
	: "cc");							\
									\
	return result;							\
}

#define atomic_add_return_relaxed	atomic_add_return_relaxed
#define atomic_sub_return_relaxed	atomic_sub_return_relaxed
#define atomic_fetch_add_relaxed	atomic_fetch_add_relaxed
#define atomic_fetch_sub_relaxed	atomic_fetch_sub_relaxed

#define atomic_fetch_and_relaxed	atomic_fetch_and_relaxed
#define atomic_fetch_andnot_relaxed	atomic_fetch_andnot_relaxed
#define atomic_fetch_or_relaxed		atomic_fetch_or_relaxed
#define atomic_fetch_xor_relaxed	atomic_fetch_xor_relaxed

static inline int atomic_cmpxchg_relaxed(atomic_t *ptr, int old, int new)
{
	int oldval;
	unsigned long res;

prefetchw(&ptr->counter);

do {
		__asm__ __volatile__("@ atomic_cmpxchg\n"
		"ldrex	%1, [%3]\n"
		"mov	%0, #0\n"
		"teq	%1, %4\n"
		"strexeq %0, %5, [%3]\n"
		    : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
		    : "r" (&ptr->counter), "Ir" (old), "r" (new)
		    : "cc");
	} while (res);

return oldval;
}
#define atomic_cmpxchg_relaxed		atomic_cmpxchg_relaxed

static inline int __atomic_add_unless(atomic_t *v, int a, int u)
{
	int oldval, newval;
	unsigned long tmp;

smp_mb();
	prefetchw(&v->counter);

__asm__ __volatile__ ("@ atomic_add_unless\n"
"1:	ldrex	%0, [%4]\n"
"	teq	%0, %5\n"
"	beq	2f\n"
"	add	%1, %0, %6\n"
"	strex	%2, %1, [%4]\n"
"	teq	%2, #0\n"
"	bne	1b\n"
"2:"
	: "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter), "r" (u), "r" (a)
	: "cc");

if (oldval != u)
		smp_mb();

return oldval;
}

#else /* ARM_ARCH_6 */

#ifdef CONFIG_SMP
#error SMP not supported on pre-ARMv6 CPUs
#endif

#define ATOMIC_OP(op, c_op, asm_op)					\
static inline void atomic_##op(int i, atomic_t *v)			\
{									\
	unsigned long flags;						\
									\
	raw_local_irq_save(flags);					\
	v->counter c_op i;						\
	raw_local_irq_restore(flags);					\
}									\

#define ATOMIC_OP_RETURN(op, c_op, asm_op)				\
static inline int atomic_##op##_return(int i, atomic_t *v)		\
{									\
	unsigned long flags;						\
	int val;							\
									\
	raw_local_irq_save(flags);					\
	v->counter c_op i;						\
	val = v->counter;						\
	raw_local_irq_restore(flags);					\
									\
	return val;							\
}

#define ATOMIC_FETCH_OP(op, c_op, asm_op)				\
static inline int atomic_fetch_##op(int i, atomic_t *v)			\
{									\
	unsigned long flags;						\
	int val;							\
									\
	raw_local_irq_save(flags);					\
	val = v->counter;						\
	v->counter c_op i;						\
	raw_local_irq_restore(flags);					\
									\
	return val;							\
}

static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
{
	int ret;
	unsigned long flags;

raw_local_irq_save(flags);
	ret = v->counter;
	if (likely(ret == old))
		v->counter = new;
	raw_local_irq_restore(flags);

return ret;
}

static inline int __atomic_add_unless(atomic_t *v, int a, int u)
{
	int c, old;

c = atomic_read(v);
	while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
		c = old;
	return c;
}

#endif /* __LINUX_ARM_ARCH__ */

#define ATOMIC_OPS(op, c_op, asm_op)					\
	ATOMIC_OP(op, c_op, asm_op)					\
	ATOMIC_OP_RETURN(op, c_op, asm_op)				\
	ATOMIC_FETCH_OP(op, c_op, asm_op)

ATOMIC_OPS(add, +=, add)
ATOMIC_OPS(sub, -=, sub)

#define atomic_andnot atomic_andnot

#undef ATOMIC_OPS
#define ATOMIC_OPS(op, c_op, asm_op)					\
	ATOMIC_OP(op, c_op, asm_op)					\
	ATOMIC_FETCH_OP(op, c_op, asm_op)

ATOMIC_OPS(and, &=, and)
ATOMIC_OPS(andnot, &= ~, bic)
ATOMIC_OPS(or,  |=, orr)
ATOMIC_OPS(xor, ^=, eor)

#undef ATOMIC_OPS
#undef ATOMIC_FETCH_OP
#undef ATOMIC_OP_RETURN
#undef ATOMIC_OP

#define atomic_xchg(v, new) (xchg(&((v)->counter), new))

#define atomic_inc(v)		atomic_add(1, v)
#define atomic_dec(v)		atomic_sub(1, v)

#define atomic_inc_and_test(v)	(atomic_add_return(1, v) == 0)
#define atomic_dec_and_test(v)	(atomic_sub_return(1, v) == 0)
#define atomic_inc_return_relaxed(v)    (atomic_add_return_relaxed(1, v))
#define atomic_dec_return_relaxed(v)    (atomic_sub_return_relaxed(1, v))
#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)

#define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)

#ifndef CONFIG_GENERIC_ATOMIC64
typedef struct {
	long long counter;
} atomic64_t;

#define ATOMIC64_INIT(i) { (i) }

#ifdef CONFIG_ARM_LPAE
static inline long long atomic64_read(const atomic64_t *v)
{
	long long result;

__asm__ __volatile__("@ atomic64_read\n"
"	ldrd	%0, %H0, [%1]"
	: "=&r" (result)
	: "r" (&v->counter), "Qo" (v->counter)
	);

return result;
}

static inline void atomic64_set(atomic64_t *v, long long i)
{
	__asm__ __volatile__("@ atomic64_set\n"
"	strd	%2, %H2, [%1]"
	: "=Qo" (v->counter)
	: "r" (&v->counter), "r" (i)
	);
}
#else
static inline long long atomic64_read(const atomic64_t *v)
{
	long long result;

__asm__ __volatile__("@ atomic64_read\n"
"	ldrexd	%0, %H0, [%1]"
	: "=&r" (result)
	: "r" (&v->counter), "Qo" (v->counter)
	);

return result;
}

static inline void atomic64_set(atomic64_t *v, long long i)
{
	long long tmp;

prefetchw(&v->counter);
	__asm__ __volatile__("@ atomic64_set\n"
"1:	ldrexd	%0, %H0, [%2]\n"
"	strexd	%0, %3, %H3, [%2]\n"
"	teq	%0, #0\n"
"	bne	1b"
	: "=&r" (tmp), "=Qo" (v->counter)
	: "r" (&v->counter), "r" (i)
	: "cc");
}
#endif

#define ATOMIC64_OP(op, op1, op2)					\
static inline void atomic64_##op(long long i, atomic64_t *v)		\
{									\
	long long result;						\
	unsigned long tmp;						\
									\
	prefetchw(&v->counter);						\
	__asm__ __volatile__("@ atomic64_" #op "\n"			\
"1:	ldrexd	%0, %H0, [%3]\n"					\
"	" #op1 " %Q0, %Q0, %Q4\n"					\
"	" #op2 " %R0, %R0, %R4\n"					\
"	strexd	%1, %0, %H0, [%3]\n"					\
"	teq	%1, #0\n"						\
"	bne	1b"							\
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)		\
	: "r" (&v->counter), "r" (i)					\
	: "cc");							\
}									\

#define ATOMIC64_OP_RETURN(op, op1, op2)				\
static inline long long							\
atomic64_##op##_return_relaxed(long long i, atomic64_t *v)		\
{									\
	long long result;						\
	unsigned long tmp;						\
									\
	prefetchw(&v->counter);						\
									\
	__asm__ __volatile__("@ atomic64_" #op "_return\n"		\
"1:	ldrexd	%0, %H0, [%3]\n"					\
"	" #op1 " %Q0, %Q0, %Q4\n"					\
"	" #op2 " %R0, %R0, %R4\n"					\
"	strexd	%1, %0, %H0, [%3]\n"					\
"	teq	%1, #0\n"						\
"	bne	1b"							\
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)		\
	: "r" (&v->counter), "r" (i)					\
	: "cc");							\
									\
	return result;							\
}

#define ATOMIC64_FETCH_OP(op, op1, op2)					\
static inline long long							\
atomic64_fetch_##op##_relaxed(long long i, atomic64_t *v)		\
{									\
	long long result, val;						\
	unsigned long tmp;						\
									\
	prefetchw(&v->counter);						\
									\
	__asm__ __volatile__("@ atomic64_fetch_" #op "\n"		\
"1:	ldrexd	%0, %H0, [%4]\n"					\
"	" #op1 " %Q1, %Q0, %Q5\n"					\
"	" #op2 " %R1, %R0, %R5\n"					\
"	strexd	%2, %1, %H1, [%4]\n"					\
"	teq	%2, #0\n"						\
"	bne	1b"							\
	: "=&r" (result), "=&r" (val), "=&r" (tmp), "+Qo" (v->counter)	\
	: "r" (&v->counter), "r" (i)					\
	: "cc");							\
									\
	return result;							\
}

#define ATOMIC64_OPS(op, op1, op2)					\
	ATOMIC64_OP(op, op1, op2)					\
	ATOMIC64_OP_RETURN(op, op1, op2)				\
	ATOMIC64_FETCH_OP(op, op1, op2)

ATOMIC64_OPS(add, adds, adc)
ATOMIC64_OPS(sub, subs, sbc)

#define atomic64_add_return_relaxed	atomic64_add_return_relaxed
#define atomic64_sub_return_relaxed	atomic64_sub_return_relaxed
#define atomic64_fetch_add_relaxed	atomic64_fetch_add_relaxed
#define atomic64_fetch_sub_relaxed	atomic64_fetch_sub_relaxed

#undef ATOMIC64_OPS
#define ATOMIC64_OPS(op, op1, op2)					\
	ATOMIC64_OP(op, op1, op2)					\
	ATOMIC64_FETCH_OP(op, op1, op2)

#define atomic64_andnot atomic64_andnot

ATOMIC64_OPS(and, and, and)
ATOMIC64_OPS(andnot, bic, bic)
ATOMIC64_OPS(or,  orr, orr)
ATOMIC64_OPS(xor, eor, eor)

#define atomic64_fetch_and_relaxed	atomic64_fetch_and_relaxed
#define atomic64_fetch_andnot_relaxed	atomic64_fetch_andnot_relaxed
#define atomic64_fetch_or_relaxed	atomic64_fetch_or_relaxed
#define atomic64_fetch_xor_relaxed	atomic64_fetch_xor_relaxed

#undef ATOMIC64_OPS
#undef ATOMIC64_FETCH_OP
#undef ATOMIC64_OP_RETURN
#undef ATOMIC64_OP

static inline long long
atomic64_cmpxchg_relaxed(atomic64_t *ptr, long long old, long long new)
{
	long long oldval;
	unsigned long res;

prefetchw(&ptr->counter);

do {
		__asm__ __volatile__("@ atomic64_cmpxchg\n"
		"ldrexd		%1, %H1, [%3]\n"
		"mov		%0, #0\n"
		"teq		%1, %4\n"
		"teqeq		%H1, %H4\n"
		"strexdeq	%0, %5, %H5, [%3]"
		: "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
		: "r" (&ptr->counter), "r" (old), "r" (new)
		: "cc");
	} while (res);

return oldval;
}
#define atomic64_cmpxchg_relaxed	atomic64_cmpxchg_relaxed

static inline long long atomic64_xchg_relaxed(atomic64_t *ptr, long long new)
{
	long long result;
	unsigned long tmp;

prefetchw(&ptr->counter);

__asm__ __volatile__("@ atomic64_xchg\n"
"1:	ldrexd	%0, %H0, [%3]\n"
"	strexd	%1, %4, %H4, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b"
	: "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
	: "r" (&ptr->counter), "r" (new)
	: "cc");

return result;
}
#define atomic64_xchg_relaxed		atomic64_xchg_relaxed

static inline long long atomic64_dec_if_positive(atomic64_t *v)
{
	long long result;
	unsigned long tmp;

smp_mb();
	prefetchw(&v->counter);

__asm__ __volatile__("@ atomic64_dec_if_positive\n"
"1:	ldrexd	%0, %H0, [%3]\n"
"	subs	%Q0, %Q0, #1\n"
"	sbc	%R0, %R0, #0\n"
"	teq	%R0, #0\n"
"	bmi	2f\n"
"	strexd	%1, %0, %H0, [%3]\n"
"	teq	%1, #0\n"
"	bne	1b\n"
"2:"
	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter)
	: "cc");

smp_mb();

return result;
}

static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
{
	long long val;
	unsigned long tmp;
	int ret = 1;

smp_mb();
	prefetchw(&v->counter);

__asm__ __volatile__("@ atomic64_add_unless\n"
"1:	ldrexd	%0, %H0, [%4]\n"
"	teq	%0, %5\n"
"	teqeq	%H0, %H5\n"
"	moveq	%1, #0\n"
"	beq	2f\n"
"	adds	%Q0, %Q0, %Q6\n"
"	adc	%R0, %R0, %R6\n"
"	strexd	%2, %0, %H0, [%4]\n"
"	teq	%2, #0\n"
"	bne	1b\n"
"2:"
	: "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter)
	: "r" (&v->counter), "r" (u), "r" (a)
	: "cc");

if (ret)
		smp_mb();

return ret;
}

#define atomic64_add_negative(a, v)	(atomic64_add_return((a), (v)) < 0)
#define atomic64_inc(v)			atomic64_add(1LL, (v))
#define atomic64_inc_return_relaxed(v)	atomic64_add_return_relaxed(1LL, (v))
#define atomic64_inc_and_test(v)	(atomic64_inc_return(v) == 0)
#define atomic64_sub_and_test(a, v)	(atomic64_sub_return((a), (v)) == 0)
#define atomic64_dec(v)			atomic64_sub(1LL, (v))
#define atomic64_dec_return_relaxed(v)	atomic64_sub_return_relaxed(1LL, (v))
#define atomic64_dec_and_test(v)	(atomic64_dec_return((v)) == 0)
#define atomic64_inc_not_zero(v)	atomic64_add_unless((v), 1LL, 0LL)

#endif /* !CONFIG_GENERIC_ATOMIC64 */
#endif
#endif