OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:15 AM	rwxr-xr-x
📁 ac97	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 ac97_codec.h	16.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 aci.h	2.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ad1816a.h	5.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ad1843.h	1.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 adau1373.h	699 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 aess.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ak4113.h	10.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ak4114.h	10.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ak4117.h	9.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ak4531_codec.h	3.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ak4641.h	622 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ak4xxx-adda.h	3.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 alc5623.h	536 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asequencer.h	3.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asound.h	1.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asoundef.h	16.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compress_driver.h	6.93 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 control.h	8.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 core.h	13.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cs35l33.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cs35l34.h	887 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cs35l35.h	2.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cs4231-regs.h	8.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cs4271.h	1.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cs42l52.h	738 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cs42l56.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cs42l73.h	507 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cs8403.h	8.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cs8427.h	10.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 da7213.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 da7218.h	2.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 da7219-aad.h	2.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 da7219.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 da9055.h	914 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 designware_i2s.h	2.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dmaengine_pcm.h	6.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emu10k1.h	89.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emu10k1_synth.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emu8000.h	4.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emu8000_reg.h	10.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emux_legacy.h	5.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emux_synth.h	7.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 es1688.h	3.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gus.h	20.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hda_chmap.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hda_hwdep.h	1.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hda_i915.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hda_register.h	10 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hda_regmap.h	6.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hda_verbs.h	16.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hdaudio.h	18.39 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hdaudio_ext.h	6.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hdmi-codec.h	2.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwdep.h	2.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c.h	3.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 info.h	7.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 initval.h	3.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jack.h	3.75 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 l3.h	524 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 max9768.h	729 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 max98088.h	1.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max98090.h	754 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 max98095.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 memalloc.h	4.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 minors.h	4.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mixer_oss.h	2.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpu401.h	4.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 omap-hdmi-audio.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 omap-pcm.h	864 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 opl3.h	12.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 opl4.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pcm-indirect.h	5.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pcm.h	47.51 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pcm_drm_eld.h	183 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pcm_iec958.h	332 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pcm_oss.h	2.69 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pcm_params.h	9.03 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pt2258.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pxa2xx-lib.h	1.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rawmidi.h	6.17 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 rt286.h	460 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rt298.h	519 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rt5514.h	478 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rt5640.h	648 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rt5645.h	738 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rt5651.h	581 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rt5659.h	1003 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rt5660.h	724 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rt5663.h	622 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rt5665.h	907 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rt5670.h	679 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 s3c24xx_uda134x.h	229 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sb.h	10.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sb16_csp.h	2.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seq_device.h	2.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seq_kernel.h	3.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seq_midi_emul.h	7.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seq_midi_event.h	2.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seq_oss.h	2.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seq_oss_legacy.h	1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seq_virmidi.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sh_dac_audio.h	587 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sh_fsi.h	847 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 simple_card.h	683 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 simple_card_utils.h	3.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 snd_wavefront.h	5.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 soc-acpi-intel-match.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 soc-acpi.h	3.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 soc-dai.h	11.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 soc-dapm.h	30.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 soc-dpcm.h	4.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 soc-topology.h	5.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 soc.h	63.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 soundfont.h	4.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spear_dma.h	1003 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spear_spdif.h	1010 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sta32x.h	1.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sta350.h	1.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tas2552-plat.h	678 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tas5086.h	210 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tea6330t.h	1.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timer.h	5.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlv.h	2.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlv320aic32x4.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlv320aic3x.h	1.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlv320dac33-plat.h	720 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tpa6130a2-plat.h	900 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uda134x.h	597 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uda1380.h	481 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 util_mem.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vx_core.h	15.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 wavefront.h	18.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 wm0010.h	679 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 wm1250-ev1.h	656 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 wm2000.h	625 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 wm2200.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 wm5100.h	1.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 wm8903.h	15.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 wm8904.h	7.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 wm8955.h	662 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 wm8960.h	603 bytes	01/28/2018 09:20:33 PM	rw-r--r--
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📄 wm9081.h	661 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 wm9090.h	780 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 wss.h	8.44 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: wm8903.h

/*
 * linux/sound/wm8903.h -- Platform data for WM8903
 *
 * Copyright 2010 Wolfson Microelectronics. PLC.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __LINUX_SND_WM8903_H
#define __LINUX_SND_WM8903_H

/*
 * Used to enable configuration of a GPIO to all zeros; a gpio_cfg value of
 * zero in platform data means "don't touch this pin".
 */
#define WM8903_GPIO_CONFIG_ZERO 0x8000

/*
 * R6 (0x06) - Mic Bias Control 0
 */
#define WM8903_MICDET_THR_MASK                  0x0030  /* MICDET_THR - [5:4] */
#define WM8903_MICDET_THR_SHIFT                      4  /* MICDET_THR - [5:4] */
#define WM8903_MICDET_THR_WIDTH                      2  /* MICDET_THR - [5:4] */
#define WM8903_MICSHORT_THR_MASK                0x000C  /* MICSHORT_THR - [3:2] */
#define WM8903_MICSHORT_THR_SHIFT                    2  /* MICSHORT_THR - [3:2] */
#define WM8903_MICSHORT_THR_WIDTH                    2  /* MICSHORT_THR - [3:2] */
#define WM8903_MICDET_ENA                       0x0002  /* MICDET_ENA */
#define WM8903_MICDET_ENA_MASK                  0x0002  /* MICDET_ENA */
#define WM8903_MICDET_ENA_SHIFT                      1  /* MICDET_ENA */
#define WM8903_MICDET_ENA_WIDTH                      1  /* MICDET_ENA */
#define WM8903_MICBIAS_ENA                      0x0001  /* MICBIAS_ENA */
#define WM8903_MICBIAS_ENA_MASK                 0x0001  /* MICBIAS_ENA */
#define WM8903_MICBIAS_ENA_SHIFT                     0  /* MICBIAS_ENA */
#define WM8903_MICBIAS_ENA_WIDTH                     1  /* MICBIAS_ENA */

/*
 * WM8903_GPn_FN values
 *
 * See datasheets for list of valid values per pin
 */
#define WM8903_GPn_FN_GPIO_OUTPUT                    0
#define WM8903_GPn_FN_BCLK                           1
#define WM8903_GPn_FN_IRQ_OUTPT                      2
#define WM8903_GPn_FN_GPIO_INPUT                     3
#define WM8903_GPn_FN_MICBIAS_CURRENT_DETECT         4
#define WM8903_GPn_FN_MICBIAS_SHORT_DETECT           5
#define WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT             6
#define WM8903_GPn_FN_FLL_LOCK_OUTPUT                8
#define WM8903_GPn_FN_FLL_CLOCK_OUTPUT               9

/*
 * R116 (0x74) - GPIO Control 1
 */
#define WM8903_GP1_FN_MASK                      0x1F00  /* GP1_FN - [12:8] */
#define WM8903_GP1_FN_SHIFT                          8  /* GP1_FN - [12:8] */
#define WM8903_GP1_FN_WIDTH                          5  /* GP1_FN - [12:8] */
#define WM8903_GP1_DIR                          0x0080  /* GP1_DIR */
#define WM8903_GP1_DIR_MASK                     0x0080  /* GP1_DIR */
#define WM8903_GP1_DIR_SHIFT                         7  /* GP1_DIR */
#define WM8903_GP1_DIR_WIDTH                         1  /* GP1_DIR */
#define WM8903_GP1_OP_CFG                       0x0040  /* GP1_OP_CFG */
#define WM8903_GP1_OP_CFG_MASK                  0x0040  /* GP1_OP_CFG */
#define WM8903_GP1_OP_CFG_SHIFT                      6  /* GP1_OP_CFG */
#define WM8903_GP1_OP_CFG_WIDTH                      1  /* GP1_OP_CFG */
#define WM8903_GP1_IP_CFG                       0x0020  /* GP1_IP_CFG */
#define WM8903_GP1_IP_CFG_MASK                  0x0020  /* GP1_IP_CFG */
#define WM8903_GP1_IP_CFG_SHIFT                      5  /* GP1_IP_CFG */
#define WM8903_GP1_IP_CFG_WIDTH                      1  /* GP1_IP_CFG */
#define WM8903_GP1_LVL                          0x0010  /* GP1_LVL */
#define WM8903_GP1_LVL_MASK                     0x0010  /* GP1_LVL */
#define WM8903_GP1_LVL_SHIFT                         4  /* GP1_LVL */
#define WM8903_GP1_LVL_WIDTH                         1  /* GP1_LVL */
#define WM8903_GP1_PD                           0x0008  /* GP1_PD */
#define WM8903_GP1_PD_MASK                      0x0008  /* GP1_PD */
#define WM8903_GP1_PD_SHIFT                          3  /* GP1_PD */
#define WM8903_GP1_PD_WIDTH                          1  /* GP1_PD */
#define WM8903_GP1_PU                           0x0004  /* GP1_PU */
#define WM8903_GP1_PU_MASK                      0x0004  /* GP1_PU */
#define WM8903_GP1_PU_SHIFT                          2  /* GP1_PU */
#define WM8903_GP1_PU_WIDTH                          1  /* GP1_PU */
#define WM8903_GP1_INTMODE                      0x0002  /* GP1_INTMODE */
#define WM8903_GP1_INTMODE_MASK                 0x0002  /* GP1_INTMODE */
#define WM8903_GP1_INTMODE_SHIFT                     1  /* GP1_INTMODE */
#define WM8903_GP1_INTMODE_WIDTH                     1  /* GP1_INTMODE */
#define WM8903_GP1_DB                           0x0001  /* GP1_DB */
#define WM8903_GP1_DB_MASK                      0x0001  /* GP1_DB */
#define WM8903_GP1_DB_SHIFT                          0  /* GP1_DB */
#define WM8903_GP1_DB_WIDTH                          1  /* GP1_DB */

/*
 * R117 (0x75) - GPIO Control 2
 */
#define WM8903_GP2_FN_MASK                      0x1F00  /* GP2_FN - [12:8] */
#define WM8903_GP2_FN_SHIFT                          8  /* GP2_FN - [12:8] */
#define WM8903_GP2_FN_WIDTH                          5  /* GP2_FN - [12:8] */
#define WM8903_GP2_DIR                          0x0080  /* GP2_DIR */
#define WM8903_GP2_DIR_MASK                     0x0080  /* GP2_DIR */
#define WM8903_GP2_DIR_SHIFT                         7  /* GP2_DIR */
#define WM8903_GP2_DIR_WIDTH                         1  /* GP2_DIR */
#define WM8903_GP2_OP_CFG                       0x0040  /* GP2_OP_CFG */
#define WM8903_GP2_OP_CFG_MASK                  0x0040  /* GP2_OP_CFG */
#define WM8903_GP2_OP_CFG_SHIFT                      6  /* GP2_OP_CFG */
#define WM8903_GP2_OP_CFG_WIDTH                      1  /* GP2_OP_CFG */
#define WM8903_GP2_IP_CFG                       0x0020  /* GP2_IP_CFG */
#define WM8903_GP2_IP_CFG_MASK                  0x0020  /* GP2_IP_CFG */
#define WM8903_GP2_IP_CFG_SHIFT                      5  /* GP2_IP_CFG */
#define WM8903_GP2_IP_CFG_WIDTH                      1  /* GP2_IP_CFG */
#define WM8903_GP2_LVL                          0x0010  /* GP2_LVL */
#define WM8903_GP2_LVL_MASK                     0x0010  /* GP2_LVL */
#define WM8903_GP2_LVL_SHIFT                         4  /* GP2_LVL */
#define WM8903_GP2_LVL_WIDTH                         1  /* GP2_LVL */
#define WM8903_GP2_PD                           0x0008  /* GP2_PD */
#define WM8903_GP2_PD_MASK                      0x0008  /* GP2_PD */
#define WM8903_GP2_PD_SHIFT                          3  /* GP2_PD */
#define WM8903_GP2_PD_WIDTH                          1  /* GP2_PD */
#define WM8903_GP2_PU                           0x0004  /* GP2_PU */
#define WM8903_GP2_PU_MASK                      0x0004  /* GP2_PU */
#define WM8903_GP2_PU_SHIFT                          2  /* GP2_PU */
#define WM8903_GP2_PU_WIDTH                          1  /* GP2_PU */
#define WM8903_GP2_INTMODE                      0x0002  /* GP2_INTMODE */
#define WM8903_GP2_INTMODE_MASK                 0x0002  /* GP2_INTMODE */
#define WM8903_GP2_INTMODE_SHIFT                     1  /* GP2_INTMODE */
#define WM8903_GP2_INTMODE_WIDTH                     1  /* GP2_INTMODE */
#define WM8903_GP2_DB                           0x0001  /* GP2_DB */
#define WM8903_GP2_DB_MASK                      0x0001  /* GP2_DB */
#define WM8903_GP2_DB_SHIFT                          0  /* GP2_DB */
#define WM8903_GP2_DB_WIDTH                          1  /* GP2_DB */

/*
 * R118 (0x76) - GPIO Control 3
 */
#define WM8903_GP3_FN_MASK                      0x1F00  /* GP3_FN - [12:8] */
#define WM8903_GP3_FN_SHIFT                          8  /* GP3_FN - [12:8] */
#define WM8903_GP3_FN_WIDTH                          5  /* GP3_FN - [12:8] */
#define WM8903_GP3_DIR                          0x0080  /* GP3_DIR */
#define WM8903_GP3_DIR_MASK                     0x0080  /* GP3_DIR */
#define WM8903_GP3_DIR_SHIFT                         7  /* GP3_DIR */
#define WM8903_GP3_DIR_WIDTH                         1  /* GP3_DIR */
#define WM8903_GP3_OP_CFG                       0x0040  /* GP3_OP_CFG */
#define WM8903_GP3_OP_CFG_MASK                  0x0040  /* GP3_OP_CFG */
#define WM8903_GP3_OP_CFG_SHIFT                      6  /* GP3_OP_CFG */
#define WM8903_GP3_OP_CFG_WIDTH                      1  /* GP3_OP_CFG */
#define WM8903_GP3_IP_CFG                       0x0020  /* GP3_IP_CFG */
#define WM8903_GP3_IP_CFG_MASK                  0x0020  /* GP3_IP_CFG */
#define WM8903_GP3_IP_CFG_SHIFT                      5  /* GP3_IP_CFG */
#define WM8903_GP3_IP_CFG_WIDTH                      1  /* GP3_IP_CFG */
#define WM8903_GP3_LVL                          0x0010  /* GP3_LVL */
#define WM8903_GP3_LVL_MASK                     0x0010  /* GP3_LVL */
#define WM8903_GP3_LVL_SHIFT                         4  /* GP3_LVL */
#define WM8903_GP3_LVL_WIDTH                         1  /* GP3_LVL */
#define WM8903_GP3_PD                           0x0008  /* GP3_PD */
#define WM8903_GP3_PD_MASK                      0x0008  /* GP3_PD */
#define WM8903_GP3_PD_SHIFT                          3  /* GP3_PD */
#define WM8903_GP3_PD_WIDTH                          1  /* GP3_PD */
#define WM8903_GP3_PU                           0x0004  /* GP3_PU */
#define WM8903_GP3_PU_MASK                      0x0004  /* GP3_PU */
#define WM8903_GP3_PU_SHIFT                          2  /* GP3_PU */
#define WM8903_GP3_PU_WIDTH                          1  /* GP3_PU */
#define WM8903_GP3_INTMODE                      0x0002  /* GP3_INTMODE */
#define WM8903_GP3_INTMODE_MASK                 0x0002  /* GP3_INTMODE */
#define WM8903_GP3_INTMODE_SHIFT                     1  /* GP3_INTMODE */
#define WM8903_GP3_INTMODE_WIDTH                     1  /* GP3_INTMODE */
#define WM8903_GP3_DB                           0x0001  /* GP3_DB */
#define WM8903_GP3_DB_MASK                      0x0001  /* GP3_DB */
#define WM8903_GP3_DB_SHIFT                          0  /* GP3_DB */
#define WM8903_GP3_DB_WIDTH                          1  /* GP3_DB */

/*
 * R119 (0x77) - GPIO Control 4
 */
#define WM8903_GP4_FN_MASK                      0x1F00  /* GP4_FN - [12:8] */
#define WM8903_GP4_FN_SHIFT                          8  /* GP4_FN - [12:8] */
#define WM8903_GP4_FN_WIDTH                          5  /* GP4_FN - [12:8] */
#define WM8903_GP4_DIR                          0x0080  /* GP4_DIR */
#define WM8903_GP4_DIR_MASK                     0x0080  /* GP4_DIR */
#define WM8903_GP4_DIR_SHIFT                         7  /* GP4_DIR */
#define WM8903_GP4_DIR_WIDTH                         1  /* GP4_DIR */
#define WM8903_GP4_OP_CFG                       0x0040  /* GP4_OP_CFG */
#define WM8903_GP4_OP_CFG_MASK                  0x0040  /* GP4_OP_CFG */
#define WM8903_GP4_OP_CFG_SHIFT                      6  /* GP4_OP_CFG */
#define WM8903_GP4_OP_CFG_WIDTH                      1  /* GP4_OP_CFG */
#define WM8903_GP4_IP_CFG                       0x0020  /* GP4_IP_CFG */
#define WM8903_GP4_IP_CFG_MASK                  0x0020  /* GP4_IP_CFG */
#define WM8903_GP4_IP_CFG_SHIFT                      5  /* GP4_IP_CFG */
#define WM8903_GP4_IP_CFG_WIDTH                      1  /* GP4_IP_CFG */
#define WM8903_GP4_LVL                          0x0010  /* GP4_LVL */
#define WM8903_GP4_LVL_MASK                     0x0010  /* GP4_LVL */
#define WM8903_GP4_LVL_SHIFT                         4  /* GP4_LVL */
#define WM8903_GP4_LVL_WIDTH                         1  /* GP4_LVL */
#define WM8903_GP4_PD                           0x0008  /* GP4_PD */
#define WM8903_GP4_PD_MASK                      0x0008  /* GP4_PD */
#define WM8903_GP4_PD_SHIFT                          3  /* GP4_PD */
#define WM8903_GP4_PD_WIDTH                          1  /* GP4_PD */
#define WM8903_GP4_PU                           0x0004  /* GP4_PU */
#define WM8903_GP4_PU_MASK                      0x0004  /* GP4_PU */
#define WM8903_GP4_PU_SHIFT                          2  /* GP4_PU */
#define WM8903_GP4_PU_WIDTH                          1  /* GP4_PU */
#define WM8903_GP4_INTMODE                      0x0002  /* GP4_INTMODE */
#define WM8903_GP4_INTMODE_MASK                 0x0002  /* GP4_INTMODE */
#define WM8903_GP4_INTMODE_SHIFT                     1  /* GP4_INTMODE */
#define WM8903_GP4_INTMODE_WIDTH                     1  /* GP4_INTMODE */
#define WM8903_GP4_DB                           0x0001  /* GP4_DB */
#define WM8903_GP4_DB_MASK                      0x0001  /* GP4_DB */
#define WM8903_GP4_DB_SHIFT                          0  /* GP4_DB */
#define WM8903_GP4_DB_WIDTH                          1  /* GP4_DB */

/*
 * R120 (0x78) - GPIO Control 5
 */
#define WM8903_GP5_FN_MASK                      0x1F00  /* GP5_FN - [12:8] */
#define WM8903_GP5_FN_SHIFT                          8  /* GP5_FN - [12:8] */
#define WM8903_GP5_FN_WIDTH                          5  /* GP5_FN - [12:8] */
#define WM8903_GP5_DIR                          0x0080  /* GP5_DIR */
#define WM8903_GP5_DIR_MASK                     0x0080  /* GP5_DIR */
#define WM8903_GP5_DIR_SHIFT                         7  /* GP5_DIR */
#define WM8903_GP5_DIR_WIDTH                         1  /* GP5_DIR */
#define WM8903_GP5_OP_CFG                       0x0040  /* GP5_OP_CFG */
#define WM8903_GP5_OP_CFG_MASK                  0x0040  /* GP5_OP_CFG */
#define WM8903_GP5_OP_CFG_SHIFT                      6  /* GP5_OP_CFG */
#define WM8903_GP5_OP_CFG_WIDTH                      1  /* GP5_OP_CFG */
#define WM8903_GP5_IP_CFG                       0x0020  /* GP5_IP_CFG */
#define WM8903_GP5_IP_CFG_MASK                  0x0020  /* GP5_IP_CFG */
#define WM8903_GP5_IP_CFG_SHIFT                      5  /* GP5_IP_CFG */
#define WM8903_GP5_IP_CFG_WIDTH                      1  /* GP5_IP_CFG */
#define WM8903_GP5_LVL                          0x0010  /* GP5_LVL */
#define WM8903_GP5_LVL_MASK                     0x0010  /* GP5_LVL */
#define WM8903_GP5_LVL_SHIFT                         4  /* GP5_LVL */
#define WM8903_GP5_LVL_WIDTH                         1  /* GP5_LVL */
#define WM8903_GP5_PD                           0x0008  /* GP5_PD */
#define WM8903_GP5_PD_MASK                      0x0008  /* GP5_PD */
#define WM8903_GP5_PD_SHIFT                          3  /* GP5_PD */
#define WM8903_GP5_PD_WIDTH                          1  /* GP5_PD */
#define WM8903_GP5_PU                           0x0004  /* GP5_PU */
#define WM8903_GP5_PU_MASK                      0x0004  /* GP5_PU */
#define WM8903_GP5_PU_SHIFT                          2  /* GP5_PU */
#define WM8903_GP5_PU_WIDTH                          1  /* GP5_PU */
#define WM8903_GP5_INTMODE                      0x0002  /* GP5_INTMODE */
#define WM8903_GP5_INTMODE_MASK                 0x0002  /* GP5_INTMODE */
#define WM8903_GP5_INTMODE_SHIFT                     1  /* GP5_INTMODE */
#define WM8903_GP5_INTMODE_WIDTH                     1  /* GP5_INTMODE */
#define WM8903_GP5_DB                           0x0001  /* GP5_DB */
#define WM8903_GP5_DB_MASK                      0x0001  /* GP5_DB */
#define WM8903_GP5_DB_SHIFT                          0  /* GP5_DB */
#define WM8903_GP5_DB_WIDTH                          1  /* GP5_DB */

#define WM8903_NUM_GPIO 5

struct wm8903_platform_data {
	bool irq_active_low;   /* Set if IRQ active low, default high */

/* Default register value for R6 (Mic bias), used to configure
	 * microphone detection.  In conjunction with gpio_cfg this
	 * can be used to route the microphone status signals out onto
	 * the GPIOs for use with snd_soc_jack_add_gpios().
	 */
	u16 micdet_cfg;

int micdet_delay;      /* Delay after microphone detection (ms) */

int gpio_base;
	u32 gpio_cfg[WM8903_NUM_GPIO]; /* Default register values for GPIO pin mux */
};

#endif