OXIESEC PANEL
- Current Dir:
/
/
usr
/
src
/
linux-headers-4.15.0-213
/
include
/
linux
/
mfd
Server IP: 139.59.38.164
Upload:
Create Dir:
Name
Size
Modified
Perms
📁
..
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
88pm80x.h
9.99 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
88pm860x.h
13.33 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
aat2870.h
4.54 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ab3100.h
4.16 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
abx500
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
abx500.h
11.72 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ac100.h
6.12 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
adp5520.h
8.3 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
altera-a10sr.h
3.42 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
arizona
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
as3711.h
2.9 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
as3722.h
15.11 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
asic3.h
12.22 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
atmel-hlcdc.h
2.57 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
axp20x.h
16.91 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bcm590xx.h
831 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
bd9571mwv.h
3.37 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
core.h
4.03 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cros_ec.h
10.37 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cros_ec_commands.h
84.45 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cros_ec_lpc_mec.h
2.77 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cros_ec_lpc_reg.h
1.9 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
da8xx-cfgchip.h
7.33 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
da903x.h
7.05 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
da9052
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
da9055
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
da9062
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
da9063
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
da9150
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
davinci_voicecodec.h
3.25 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
db8500-prcmu.h
21.68 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
dbx500-prcmu.h
14.34 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
dln2.h
3.53 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
dm355evm_msp.h
2.81 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ds1wm.h
817 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
ezx-pcap.h
7.75 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hi6421-pmic.h
1.3 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hi655x-pmic.h
2.03 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
htc-pasic3.h
1.2 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
imx25-tsadc.h
4.86 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
intel_msic.h
15.99 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
intel_soc_pmic.h
1.17 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
intel_soc_pmic_bxtwc.h
2 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ipaq-micro.h
3.66 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
janz.h
1.03 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
kempld.h
4.16 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
lm3533.h
2.59 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
lp3943.h
2.68 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
lp873x.h
8.69 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
lp87565.h
7.68 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
lp8788-isink.h
1.19 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
lp8788.h
8.84 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
lpc_ich.h
1.23 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
max14577-private.h
15.86 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
max14577.h
2.68 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
max77620.h
10.87 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
max77686-private.h
13.21 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
max77686.h
2.65 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
max77693-common.h
1.27 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
max77693-private.h
17.95 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
max77693.h
2.24 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
max77843-private.h
15.43 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
max8907.h
7.52 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
max8925.h
7.18 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
max8997-private.h
12.43 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
max8997.h
6.04 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
max8998-private.h
5.01 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
max8998.h
3.56 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mc13783.h
2.83 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mc13892.h
938 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
mc13xxx.h
7.65 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
mcp.h
1.77 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
menelaus.h
1.25 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
motorola-cpcap.h
12.5 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
mt6323
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
mt6397
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
mxs-lradc.h
6.05 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
palmas.h
149.07 KB
06/16/2023 05:32:39 PM
rw-r--r--
📁
pcf50633
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
qcom_rpm.h
293 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
rc5t583.h
9.82 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
rdc321x.h
591 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
retu.h
723 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
rk808.h
12.51 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
rn5t618.h
7.34 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
rt5033-private.h
7.84 KB
06/16/2023 05:32:39 PM
rw-r--r--
📄
rt5033.h
1.21 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
samsung
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
si476x-core.h
15.24 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
si476x-platform.h
6.45 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
si476x-reports.h
4.89 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
sky81452.h
990 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
smsc.h
2.85 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
sta2x11-mfd.h
18.72 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
stm32-lptimer.h
1.81 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
stm32-timers.h
3.07 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
stmpe.h
3.38 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
stw481x.h
1.41 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
sun4i-gpadc.h
3.62 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
syscon
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
syscon.h
1.41 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
t7l66xb.h
771 bytes
06/16/2023 05:32:39 PM
rw-r--r--
📄
tc3589x.h
3.91 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tc6387xb.h
516 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
tc6393xb.h
1.51 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ti-lmu-register.h
7.43 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ti-lmu.h
1.78 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ti_am335x_tscadc.h
5.72 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tmio.h
4.6 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tps6105x.h
3.03 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tps65010.h
6.53 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tps6507x.h
4.94 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tps65086.h
3.5 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tps65090.h
4.35 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tps65217.h
8.24 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tps65218.h
7.84 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tps6586x.h
2.71 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tps65910.h
30.59 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tps65912.h
9.91 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tps68470.h
3.33 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tps80031.h
19.59 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
twl.h
25.58 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
twl4030-audio.h
8.54 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
twl6040.h
7.16 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ucb1x00.h
6.57 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
viperboard.h
2.95 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
wl1273-core.h
8.3 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
wm831x
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📁
wm8350
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
wm8400-audio.h
69.8 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
wm8400-private.h
57.98 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
wm8400.h
1.18 KB
01/28/2018 09:20:33 PM
rw-r--r--
📁
wm8994
-
05/09/2024 07:14:16 AM
rwxr-xr-x
📄
wm97xx.h
576 bytes
01/28/2018 09:20:33 PM
rw-r--r--
Editing: stm32-timers.h
Close
/* * Copyright (C) STMicroelectronics 2016 * * Author: Benjamin Gaignard <benjamin.gaignard@st.com> * * License terms: GNU General Public License (GPL), version 2 */ #ifndef _LINUX_STM32_GPTIMER_H_ #define _LINUX_STM32_GPTIMER_H_ #include <linux/clk.h> #include <linux/regmap.h> #define TIM_CR1 0x00 /* Control Register 1 */ #define TIM_CR2 0x04 /* Control Register 2 */ #define TIM_SMCR 0x08 /* Slave mode control reg */ #define TIM_DIER 0x0C /* DMA/interrupt register */ #define TIM_SR 0x10 /* Status register */ #define TIM_EGR 0x14 /* Event Generation Reg */ #define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */ #define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */ #define TIM_CCER 0x20 /* Capt/Comp Enable Reg */ #define TIM_CNT 0x24 /* Counter */ #define TIM_PSC 0x28 /* Prescaler */ #define TIM_ARR 0x2c /* Auto-Reload Register */ #define TIM_CCR1 0x34 /* Capt/Comp Register 1 */ #define TIM_CCR2 0x38 /* Capt/Comp Register 2 */ #define TIM_CCR3 0x3C /* Capt/Comp Register 3 */ #define TIM_CCR4 0x40 /* Capt/Comp Register 4 */ #define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ #define TIM_CR1_CEN BIT(0) /* Counter Enable */ #define TIM_CR1_DIR BIT(4) /* Counter Direction */ #define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */ #define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */ #define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */ #define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ #define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ #define TIM_DIER_UIE BIT(0) /* Update interrupt */ #define TIM_SR_UIF BIT(0) /* Update interrupt flag */ #define TIM_EGR_UG BIT(0) /* Update Generation */ #define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ #define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ #define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ #define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ #define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ #define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ #define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ #define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ #define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) #define TIM_BDTR_BKE BIT(12) /* Break input enable */ #define TIM_BDTR_BKP BIT(13) /* Break input polarity */ #define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */ #define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ #define TIM_BDTR_BKF (BIT(16) | BIT(17) | BIT(18) | BIT(19)) #define TIM_BDTR_BK2F (BIT(20) | BIT(21) | BIT(22) | BIT(23)) #define TIM_BDTR_BK2E BIT(24) /* Break 2 input enable */ #define TIM_BDTR_BK2P BIT(25) /* Break 2 input polarity */ #define MAX_TIM_PSC 0xFFFF #define TIM_CR2_MMS_SHIFT 4 #define TIM_CR2_MMS2_SHIFT 20 #define TIM_SMCR_TS_SHIFT 4 #define TIM_BDTR_BKF_MASK 0xF #define TIM_BDTR_BKF_SHIFT 16 #define TIM_BDTR_BK2F_SHIFT 20 struct stm32_timers { struct clk *clk; struct regmap *regmap; u32 max_arr; }; #endif