OXIESEC PANEL
- Current Dir:
/
/
usr
/
src
/
linux-headers-4.15.0-213
/
arch
/
tile
/
include
/
asm
Server IP: 139.59.38.164
Upload:
Create Dir:
Name
Size
Modified
Perms
📁
..
-
05/09/2024 07:14:13 AM
rwxr-xr-x
📄
Kbuild
439 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
atomic.h
5.14 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
atomic_32.h
8.91 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
atomic_64.h
5.51 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
backtrace.h
3.98 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
barrier.h
2.89 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bitops.h
2.37 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bitops_32.h
4.01 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
bitops_64.h
2.67 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cache.h
2.6 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cacheflush.h
4.94 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
checksum.h
1.23 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
cmpxchg.h
3.47 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
compat.h
7.38 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
current.h
947 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
delay.h
1.1 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
device.h
978 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
div64.h
319 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
dma-mapping.h
1.82 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
dma.h
762 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
elf.h
5.42 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
fixmap.h
2.73 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ftrace.h
1.08 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
futex.h
4.23 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hardirq.h
1.28 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hardwall.h
1.08 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
highmem.h
2.08 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
homecache.h
4.21 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hugetlb.h
3.04 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
hv_driver.h
1.92 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ide.h
758 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
insn.h
1.79 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
io.h
12.43 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
irq.h
3.11 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
irq_work.h
283 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
irqflags.h
10.55 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
jump_label.h
1.47 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
kdebug.h
769 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
kexec.h
2.23 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
kgdb.h
1.99 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
kmap_types.h
1.02 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
kprobes.h
2.19 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
linkage.h
1.46 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mmu.h
965 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
mmu_context.h
4.5 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
mmzone.h
2.07 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
module.h
1.12 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
page.h
10.32 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pci.h
6.58 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
percpu.h
1.79 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
perf_event.h
766 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgalloc.h
4.76 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgtable.h
15.66 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgtable_32.h
4.08 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pgtable_64.h
5.11 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
pmc.h
2.15 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
processor.h
10.62 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
ptrace.h
2.96 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
sections.h
1.37 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
setup.h
1.63 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
sigframe.h
956 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
signal.h
1.07 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
smp.h
3.98 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
spinlock.h
741 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
spinlock_32.h
2.9 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
spinlock_64.h
3.88 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
spinlock_types.h
1.58 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
stack.h
2.59 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
string.h
1.19 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
switch_to.h
2.75 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
syscall.h
2.88 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
syscalls.h
2.35 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
thread_info.h
5.54 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tile-desc.h
650 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
tile-desc_32.h
12.54 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tile-desc_64.h
10.83 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
timex.h
1.71 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
tlb.h
878 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
tlbflush.h
3.99 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
topology.h
1.52 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
traps.h
2.44 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
uaccess.h
12.77 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
unaligned.h
1.56 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
unistd.h
777 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
user.h
717 bytes
01/28/2018 09:20:33 PM
rw-r--r--
📄
vdso.h
1.84 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
vga.h
1.05 KB
01/28/2018 09:20:33 PM
rw-r--r--
📄
word-at-a-time.h
1.07 KB
01/28/2018 09:20:33 PM
rw-r--r--
Editing: pgtable_32.h
Close
/* * Copyright 2010 Tilera Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation, version 2. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or * NON INFRINGEMENT. See the GNU General Public License for * more details. * */ #ifndef _ASM_TILE_PGTABLE_32_H #define _ASM_TILE_PGTABLE_32_H /* * The level-1 index is defined by the huge page size. A PGD is composed * of PTRS_PER_PGD pgd_t's and is the top level of the page table. */ #define PGDIR_SHIFT HPAGE_SHIFT #define PGDIR_SIZE HPAGE_SIZE #define PGDIR_MASK (~(PGDIR_SIZE-1)) #define PTRS_PER_PGD _HV_L1_ENTRIES(HPAGE_SHIFT) #define PGD_INDEX(va) _HV_L1_INDEX(va, HPAGE_SHIFT) #define SIZEOF_PGD _HV_L1_SIZE(HPAGE_SHIFT) /* * The level-2 index is defined by the difference between the huge * page size and the normal page size. A PTE is composed of * PTRS_PER_PTE pte_t's and is the bottom level of the page table. * Note that the hypervisor docs use PTE for what we call pte_t, so * this nomenclature is somewhat confusing. */ #define PTRS_PER_PTE _HV_L2_ENTRIES(HPAGE_SHIFT, PAGE_SHIFT) #define PTE_INDEX(va) _HV_L2_INDEX(va, HPAGE_SHIFT, PAGE_SHIFT) #define SIZEOF_PTE _HV_L2_SIZE(HPAGE_SHIFT, PAGE_SHIFT) #ifndef __ASSEMBLY__ /* * Right now we initialize only a single pte table. It can be extended * easily, subsequent pte tables have to be allocated in one physical * chunk of RAM. * * HOWEVER, if we are using an allocation scheme with slop after the * end of the page table (e.g. where our L2 page tables are 2KB but * our pages are 64KB and we are allocating via the page allocator) * we can't extend it easily. */ #define LAST_PKMAP PTRS_PER_PTE #define PKMAP_BASE ((FIXADDR_BOOT_START - PAGE_SIZE*LAST_PKMAP) & PGDIR_MASK) #ifdef CONFIG_HIGHMEM # define _VMALLOC_END (PKMAP_BASE & ~(HPAGE_SIZE-1)) #else # define _VMALLOC_END (FIXADDR_START & ~(HPAGE_SIZE-1)) #endif /* * Align the vmalloc area to an L2 page table, and leave a guard page * at the beginning and end. The vmalloc code also puts in an internal * guard page between each allocation. */ #define VMALLOC_END (_VMALLOC_END - PAGE_SIZE) extern unsigned long VMALLOC_RESERVE /* = CONFIG_VMALLOC_RESERVE */; #define _VMALLOC_START (_VMALLOC_END - VMALLOC_RESERVE) #define VMALLOC_START (_VMALLOC_START + PAGE_SIZE) /* This is the maximum possible amount of lowmem. */ #define MAXMEM (_VMALLOC_START - PAGE_OFFSET) /* We have no pmd or pud since we are strictly a two-level page table */ #define __ARCH_USE_5LEVEL_HACK #include <asm-generic/pgtable-nopmd.h> static inline int pud_huge_page(pud_t pud) { return 0; } /* We don't define any pgds for these addresses. */ static inline int pgd_addr_invalid(unsigned long addr) { return addr >= MEM_HV_START; } /* * Provide versions of these routines that can be used safely when * the hypervisor may be asynchronously modifying dirty/accessed bits. * ptep_get_and_clear() matches the generic one but we provide it to * be parallel with the 64-bit code. */ #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG #define __HAVE_ARCH_PTEP_SET_WRPROTECT extern int ptep_test_and_clear_young(struct vm_area_struct *, unsigned long addr, pte_t *); extern void ptep_set_wrprotect(struct mm_struct *, unsigned long addr, pte_t *); #define __HAVE_ARCH_PTEP_GET_AND_CLEAR static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { pte_t pte = *ptep; pte_clear(_mm, addr, ptep); return pte; } /* * pmds are wrappers around pgds, which are the same as ptes. * It's often convenient to "cast" back and forth and use the pte methods, * which are the methods supplied by the hypervisor. */ #define pmd_pte(pmd) ((pmd).pud.pgd) #define pmdp_ptep(pmdp) (&(pmdp)->pud.pgd) #define pte_pmd(pte) ((pmd_t){ { (pte) } }) #endif /* __ASSEMBLY__ */ #endif /* _ASM_TILE_PGTABLE_32_H */