OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:13 AM	rwxr-xr-x
📄 Kbuild	439 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	5.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic_32.h	8.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic_64.h	5.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 backtrace.h	3.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	2.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	2.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops_32.h	4.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops_64.h	2.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	4.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	7.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	947 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	978 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 div64.h	319 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	762 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	5.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	4.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardwall.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 homecache.h	4.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	3.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hv_driver.h	1.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	758 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 insn.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	12.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	3.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_work.h	283 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	10.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	769 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	2.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	2.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	965 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	4.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	10.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	6.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	766 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	4.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	15.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable_32.h	4.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable_64.h	5.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmc.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	10.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	2.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sigframe.h	956 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	1.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	3.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	741 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_32.h	2.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_64.h	3.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	1.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stack.h	2.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	2.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	2.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscalls.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	5.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tile-desc.h	650 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tile-desc_32.h	12.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tile-desc_64.h	10.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	1.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	878 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	3.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	1.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	2.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	12.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	1.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	777 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	717 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	1.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 word-at-a-time.h	1.07 KB	01/28/2018 09:20:33 PM	rw-r--r--

Name

Size

Modified

Perms

📁 ..

05/09/2024 07:14:13 AM

rwxr-xr-x

📄 Kbuild

439 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 asm-offsets.h

35 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 atomic.h

5.14 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 atomic_32.h

8.91 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 atomic_64.h

5.51 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 backtrace.h

3.98 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 barrier.h

2.89 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bitops.h

2.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bitops_32.h

4.01 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 bitops_64.h

2.67 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cache.h

2.6 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cacheflush.h

4.94 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 checksum.h

1.23 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cmpxchg.h

3.47 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 compat.h

7.38 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 current.h

947 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 delay.h

1.1 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 device.h

978 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 div64.h

319 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma-mapping.h

1.82 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma.h

762 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 elf.h

5.42 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 fixmap.h

2.73 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 ftrace.h

1.08 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 futex.h

4.23 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hardirq.h

1.28 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hardwall.h

1.08 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 highmem.h

2.08 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 homecache.h

4.21 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hugetlb.h

3.04 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hv_driver.h

1.92 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 ide.h

758 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 insn.h

1.79 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 io.h

12.43 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irq.h

3.11 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irq_work.h

283 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 irqflags.h

10.55 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 jump_label.h

1.47 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 kdebug.h

769 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 kexec.h

2.23 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 kgdb.h

1.99 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 kmap_types.h

1.02 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 kprobes.h

2.19 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 linkage.h

1.46 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu.h

965 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu_context.h

4.5 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmzone.h

2.07 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 module.h

1.12 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 page.h

10.32 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pci.h

6.58 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 percpu.h

1.79 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 perf_event.h

766 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgalloc.h

4.76 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgtable.h

15.66 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgtable_32.h

4.08 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgtable_64.h

5.11 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pmc.h

2.15 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 processor.h

10.62 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 ptrace.h

2.96 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 sections.h

1.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 setup.h

1.63 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 sigframe.h

956 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 signal.h

1.07 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 smp.h

3.98 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock.h

741 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock_32.h

2.9 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock_64.h

3.88 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock_types.h

1.58 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 stack.h

2.59 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 string.h

1.19 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 switch_to.h

2.75 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 syscall.h

2.88 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 syscalls.h

2.35 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 thread_info.h

5.54 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 tile-desc.h

650 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 tile-desc_32.h

12.54 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 tile-desc_64.h

10.83 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 timex.h

1.71 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlb.h

878 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlbflush.h

3.99 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 topology.h

1.52 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 traps.h

2.44 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 uaccess.h

12.77 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 unaligned.h

1.56 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 unistd.h

777 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 user.h

717 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 vdso.h

1.84 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 vga.h

1.05 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 word-at-a-time.h

1.07 KB

01/28/2018 09:20:33 PM

rw-r--r--

Editing: cacheflush.h

/*
 * Copyright 2010 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 */

#ifndef _ASM_TILE_CACHEFLUSH_H
#define _ASM_TILE_CACHEFLUSH_H

#include <arch/chip.h>

/* Keep includes the same across arches.  */
#include <linux/mm.h>
#include <linux/cache.h>
#include <arch/icache.h>

/* Caches are physically-indexed and so don't need special treatment */
#define flush_cache_all()			do { } while (0)
#define flush_cache_mm(mm)			do { } while (0)
#define flush_cache_dup_mm(mm)			do { } while (0)
#define flush_cache_range(vma, start, end)	do { } while (0)
#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
#define flush_dcache_page(page)			do { } while (0)
#define flush_dcache_mmap_lock(mapping)		do { } while (0)
#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
#define flush_cache_vmap(start, end)		do { } while (0)
#define flush_cache_vunmap(start, end)		do { } while (0)
#define flush_icache_page(vma, pg)		do { } while (0)
#define flush_icache_user_range(vma, pg, adr, len)	do { } while (0)

/* Flush the icache just on this cpu */
extern void __flush_icache_range(unsigned long start, unsigned long end);

/* Flush the entire icache on this cpu. */
#define __flush_icache() __flush_icache_range(0, CHIP_L1I_CACHE_SIZE())

#ifdef CONFIG_SMP
/*
 * When the kernel writes to its own text we need to do an SMP
 * broadcast to make the L1I coherent everywhere.  This includes
 * module load and single step.
 */
extern void flush_icache_range(unsigned long start, unsigned long end);
#else
#define flush_icache_range __flush_icache_range
#endif

/*
 * An update to an executable user page requires icache flushing.
 * We could carefully update only tiles that are running this process,
 * and rely on the fact that we flush the icache on every context
 * switch to avoid doing extra work here.  But for now, I'll be
 * conservative and just do a global icache flush.
 */
static inline void copy_to_user_page(struct vm_area_struct *vma,
				     struct page *page, unsigned long vaddr,
				     void *dst, void *src, int len)
{
	memcpy(dst, src, len);
	if (vma->vm_flags & VM_EXEC) {
		flush_icache_range((unsigned long) dst,
				   (unsigned long) dst + len);
	}
}

#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
	memcpy((dst), (src), (len))

/* Flush a VA range; pads to L2 cacheline boundaries. */
static inline void __flush_buffer(void *buffer, size_t size)
{
	char *next = (char *)((long)buffer & -L2_CACHE_BYTES);
	char *finish = (char *)L2_CACHE_ALIGN((long)buffer + size);
	while (next < finish) {
		__insn_flush(next);
		next += CHIP_FLUSH_STRIDE();
	}
}

/* Flush & invalidate a VA range; pads to L2 cacheline boundaries. */
static inline void __finv_buffer(void *buffer, size_t size)
{
	char *next = (char *)((long)buffer & -L2_CACHE_BYTES);
	char *finish = (char *)L2_CACHE_ALIGN((long)buffer + size);
	while (next < finish) {
		__insn_finv(next);
		next += CHIP_FINV_STRIDE();
	}
}

/*
 * Flush a locally-homecached VA range and wait for the evicted
 * cachelines to hit memory.
 */
static inline void flush_buffer_local(void *buffer, size_t size)
{
	__flush_buffer(buffer, size);
	mb_incoherent();
}

/*
 * Flush and invalidate a locally-homecached VA range and wait for the
 * evicted cachelines to hit memory.
 */
static inline void finv_buffer_local(void *buffer, size_t size)
{
	__finv_buffer(buffer, size);
	mb_incoherent();
}

#ifdef __tilepro__
/* Invalidate a VA range; pads to L2 cacheline boundaries. */
static inline void __inv_buffer(void *buffer, size_t size)
{
	char *next = (char *)((long)buffer & -L2_CACHE_BYTES);
	char *finish = (char *)L2_CACHE_ALIGN((long)buffer + size);
	while (next < finish) {
		__insn_inv(next);
		next += CHIP_INV_STRIDE();
	}
}

/* Invalidate a VA range and wait for it to be complete. */
static inline void inv_buffer(void *buffer, size_t size)
{
	__inv_buffer(buffer, size);
	mb();
}
#endif

/*
 * Flush and invalidate a VA range that is homed remotely, waiting
 * until the memory controller holds the flushed values.  If "hfh" is
 * true, we will do a more expensive flush involving additional loads
 * to make sure we have touched all the possible home cpus of a buffer
 * that is homed with "hash for home".
 */
void finv_buffer_remote(void *buffer, size_t size, int hfh);

/*
 * On SMP systems, when the scheduler does migration-cost autodetection,
 * it needs a way to flush as much of the CPU's caches as possible:
 *
 * TODO: fill this in!
 */
static inline void sched_cacheflush(void)
{
}

#endif /* _ASM_TILE_CACHEFLUSH_H */