OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:12 AM	rwxr-xr-x
📄 Kbuild	742 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-compat.h	518 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	626 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	644 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	4.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	942 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	919 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpuinfo.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cputable.h	1 byte	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	850 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	765 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	706 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	738 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exceptions.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	1.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	641 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hash.h	2.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	2.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	1 byte	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	2.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	538 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	739 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	4.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	141 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context_mm.h	3.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	840 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	6.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-bridge.h	4.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	2.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	4.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	17.66 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 processor.h	4.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prom.h	713 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	727 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pvr.h	8.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 registers.h	1.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	256 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	637 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	630 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	629 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	4.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	402 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	714 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	2.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	9.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	871 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unwind.h	719 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	1 byte	01/28/2018 09:20:33 PM	rw-r--r--

Name

Size

Modified

Perms

📁 ..

05/09/2024 07:14:12 AM

rwxr-xr-x

📄 Kbuild

742 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 asm-compat.h

518 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 asm-offsets.h

35 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 atomic.h

626 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 cache.h

644 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 cacheflush.h

4.12 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 checksum.h

942 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 cmpxchg.h

919 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 cpuinfo.h

2.13 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cputable.h

1 byte

01/28/2018 09:20:33 PM

rw-r--r--

📄 current.h

850 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 delay.h

2.26 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma-mapping.h

765 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma.h

706 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 elf.h

738 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 entry.h

1.13 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 exceptions.h

2.08 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 fixmap.h

1.96 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 flat.h

2.26 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 ftrace.h

641 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 futex.h

2.13 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hash.h

2.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 highmem.h

2.2 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 hw_irq.h

1 byte

01/28/2018 09:20:33 PM

rw-r--r--

📄 io.h

2.05 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irq.h

538 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 irqflags.h

2.6 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 kgdb.h

739 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu.h

4.19 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu_context.h

141 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu_context_mm.h

3.91 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 module.h

840 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 page.h

6.11 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pci-bridge.h

4.57 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pci.h

2.47 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgalloc.h

4.74 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgtable.h

17.66 KB

06/16/2023 05:32:39 PM

rw-r--r--

📄 processor.h

4.11 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 prom.h

713 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 ptrace.h

727 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 pvr.h

8.72 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 registers.h

1.65 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 seccomp.h

256 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 sections.h

637 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 setup.h

1.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 string.h

630 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 switch_to.h

629 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 syscall.h

2.26 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 thread_info.h

4.01 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 timex.h

402 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlb.h

714 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlbflush.h

2.04 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 uaccess.h

9.98 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 unaligned.h

871 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 unistd.h

1.19 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 unwind.h

719 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 user.h

1 byte

01/28/2018 09:20:33 PM

rw-r--r--

Editing: futex.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_MICROBLAZE_FUTEX_H
#define _ASM_MICROBLAZE_FUTEX_H

#ifdef __KERNEL__

#include <linux/futex.h>
#include <linux/uaccess.h>
#include <asm/errno.h>

#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
({									\
	__asm__ __volatile__ (						\
			"1:	lwx	%0, %2, r0; "			\
				insn					\
			"2:	swx	%1, %2, r0;			\
				addic	%1, r0, 0;			\
				bnei	%1, 1b;				\
			3:						\
			.section .fixup,\"ax\";				\
			4:	brid	3b;				\
				addik	%1, r0, %3;			\
			.previous;					\
			.section __ex_table,\"a\";			\
			.word	1b,4b,2b,4b;				\
			.previous;"					\
	: "=&r" (oldval), "=&r" (ret)					\
	: "r" (uaddr), "i" (-EFAULT), "r" (oparg)			\
	);								\
})

static inline int
arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
{
	int oldval = 0, ret;

pagefault_disable();

switch (op) {
	case FUTEX_OP_SET:
		__futex_atomic_op("or %1,%4,%4;", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_ADD:
		__futex_atomic_op("add %1,%0,%4;", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_OR:
		__futex_atomic_op("or %1,%0,%4;", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_ANDN:
		__futex_atomic_op("andn %1,%0,%4;", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_XOR:
		__futex_atomic_op("xor %1,%0,%4;", ret, oldval, uaddr, oparg);
		break;
	default:
		ret = -ENOSYS;
	}

pagefault_enable();

if (!ret)
		*oval = oldval;

return ret;
}

static inline int
futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
			      u32 oldval, u32 newval)
{
	int ret = 0, cmp;
	u32 prev;

if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
		return -EFAULT;

__asm__ __volatile__ ("1:	lwx	%1, %3, r0;		\
					cmp	%2, %1, %4;		\
					bnei	%2, 3f;			\
				2:	swx	%5, %3, r0;		\
					addic	%2, r0, 0;		\
					bnei	%2, 1b;			\
				3:					\
				.section .fixup,\"ax\";			\
				4:	brid	3b;			\
					addik	%0, r0, %6;		\
				.previous;				\
				.section __ex_table,\"a\";		\
				.word	1b,4b,2b,4b;			\
				.previous;"				\
		: "+r" (ret), "=&r" (prev), "=&r"(cmp)	\
		: "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT));

*uval = prev;
	return ret;
}

#endif /* __KERNEL__ */

#endif