OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:12 AM	rwxr-xr-x
📄 Kbuild	865 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	2.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	705 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	3.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	2.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	947 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clock.h	3.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	1.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	911 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dscr.h	909 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	3.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	677 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	97 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	572 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	497 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 megamod-pic.h	213 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	639 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	312 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	3.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 procinfo.h	673 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	998 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	287 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	914 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 soc.h	929 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 special_insns.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	616 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	992 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	2.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscalls.h	1.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	2.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timer64.h	154 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	867 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	192 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	2.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	4.63 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: cache.h

/*
 *  Port on Texas Instruments TMS320C6x architecture
 *
 *  Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated
 *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */
#ifndef _ASM_C6X_CACHE_H
#define _ASM_C6X_CACHE_H

#include <linux/irqflags.h>
#include <linux/init.h>

/*
 * Cache line size
 */
#define L1D_CACHE_SHIFT   6
#define L1D_CACHE_BYTES   (1 << L1D_CACHE_SHIFT)

#define L1P_CACHE_SHIFT   5
#define L1P_CACHE_BYTES   (1 << L1P_CACHE_SHIFT)

#define L2_CACHE_SHIFT    7
#define L2_CACHE_BYTES    (1 << L2_CACHE_SHIFT)

/*
 * L2 used as cache
 */
#define L2MODE_SIZE	  L2MODE_256K_CACHE

/*
 * For practical reasons the L1_CACHE_BYTES defines should not be smaller than
 * the L2 line size
 */
#define L1_CACHE_SHIFT        L2_CACHE_SHIFT
#define L1_CACHE_BYTES        (1 << L1_CACHE_SHIFT)

#define L2_CACHE_ALIGN_LOW(x) \
	(((x) & ~(L2_CACHE_BYTES - 1)))
#define L2_CACHE_ALIGN_UP(x) \
	(((x) + (L2_CACHE_BYTES - 1)) & ~(L2_CACHE_BYTES - 1))
#define L2_CACHE_ALIGN_CNT(x) \
	(((x) + (sizeof(int) - 1)) & ~(sizeof(int) - 1))

#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
#define ARCH_SLAB_MINALIGN	L1_CACHE_BYTES

/*
 * This is the granularity of hardware cacheability control.
 */
#define CACHEABILITY_ALIGN	0x01000000

/*
 * Align a physical address to MAR regions
 */
#define CACHE_REGION_START(v) \
	(((u32) (v)) & ~(CACHEABILITY_ALIGN - 1))
#define CACHE_REGION_END(v) \
	(((u32) (v) + (CACHEABILITY_ALIGN - 1)) & ~(CACHEABILITY_ALIGN - 1))

extern void __init c6x_cache_init(void);

extern void enable_caching(unsigned long start, unsigned long end);
extern void disable_caching(unsigned long start, unsigned long end);

extern void L1_cache_off(void);
extern void L1_cache_on(void);

extern void L1P_cache_global_invalidate(void);
extern void L1D_cache_global_invalidate(void);
extern void L1D_cache_global_writeback(void);
extern void L1D_cache_global_writeback_invalidate(void);
extern void L2_cache_set_mode(unsigned int mode);
extern void L2_cache_global_writeback_invalidate(void);
extern void L2_cache_global_writeback(void);

extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end);
extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end);
extern void L1D_cache_block_writeback_invalidate(unsigned int start,
						 unsigned int end);
extern void L1D_cache_block_writeback(unsigned int start, unsigned int end);
extern void L2_cache_block_invalidate(unsigned int start, unsigned int end);
extern void L2_cache_block_writeback(unsigned int start, unsigned int end);
extern void L2_cache_block_writeback_invalidate(unsigned int start,
						unsigned int end);
extern void L2_cache_block_invalidate_nowait(unsigned int start,
					     unsigned int end);
extern void L2_cache_block_writeback_nowait(unsigned int start,
					    unsigned int end);

extern void L2_cache_block_writeback_invalidate_nowait(unsigned int start,
						       unsigned int end);

#endif /* _ASM_C6X_CACHE_H */