OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:18 AM	rwxr-xr-x
📄 8250_pci.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 a.out.h	354 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 acct.h	2.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 acpi.h	36.89 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 acpi_dma.h	3.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 acpi_iort.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 acpi_pmtmr.h	674 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 adb.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 adfs_fs.h	574 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 aer.h	1.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 agp_backend.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 agpgart.h	3.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ahci-remap.h	607 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ahci_platform.h	1.67 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 aio.h	673 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 alarmtimer.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 altera_jtaguart.h	379 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 altera_uart.h	397 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 amba	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 amd-iommu.h	6.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amifd.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amifdreg.h	2.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 anon_inodes.h	494 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 apm-emulation.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apm_bios.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apple-gmux.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apple_bl.h	498 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 arch_topology.h	840 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 arm-cci.h	2.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 arm-smccc.h	12.79 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 arm_sdei.h	2.33 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 asn1.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asn1_ber_bytecode.h	2.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asn1_decoder.h	675 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 assoc_array.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 assoc_array_priv.h	5.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 async.h	1.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 async_tx.h	6.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ata.h	33.18 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ata_platform.h	729 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atalk.h	4.36 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ath9k_platform.h	1.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atm.h	287 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atm_suni.h	253 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atm_tcp.h	511 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atmdev.h	10.21 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 atmel-mci.h	1.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atmel-ssc.h	9.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atmel_pdc.h	1.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atmel_tc.h	11.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	30.5 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 attribute_container.h	2.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 audit.h	17.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 auto_dev-ioctl.h	454 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 auto_fs.h	436 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 auxvec.h	304 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 average.h	2.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 avf	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 b1pcmcia.h	666 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 backing-dev-defs.h	8.53 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 backing-dev.h	13.8 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 backlight.h	5.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 badblocks.h	2.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 balloon_compaction.h	7.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcd.h	559 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bch.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcm47xx_nvram.h	1.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcm47xx_sprom.h	600 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcm47xx_wdt.h	555 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcm963xx_nvram.h	2.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcm963xx_tag.h	3.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 bcma	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 bfin_mac.h	559 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 binfmts.h	4.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bio.h	20.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bit_spinlock.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitfield.h	3.2 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitmap.h	16.68 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	6.69 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitrev.h	2.53 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bits.h	833 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 blk-cgroup.h	22.2 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 blk-mq-pci.h	247 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 blk-mq-rdma.h	232 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 blk-mq-virtio.h	288 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 blk-mq.h	9.09 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 blk_types.h	10.52 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 blkdev.h	58.96 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 blkpg.h	436 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 blktrace_api.h	3.87 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 blockgroup_lock.h	810 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bma150.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootmem.h	11.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bottom_half.h	803 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bpf-cgroup.h	4.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bpf.h	18.51 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bpf_trace.h	196 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bpf_types.h	1.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bpf_verifier.h	6.76 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 brcmphy.h	9.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bsearch.h	275 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bsg-lib.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bsg.h	773 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 btree-128.h	2.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 btree-type.h	3.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 btree.h	6.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 btrfs.h	145 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 buffer_head.h	14.04 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bug.h	1.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 build_bug.h	3.15 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bvec.h	4.39 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 byteorder	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 c2port.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheinfo.h	3.27 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 can	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 capability.h	7.6 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cb710.h	5.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cciss_ioctl.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ccp.h	18.26 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cdev.h	845 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cdrom.h	8.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 ceph	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 cfag12864b.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cgroup-defs.h	25.38 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cgroup.h	26.07 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cgroup_rdma.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cgroup_subsys.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 circ_buf.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cleancache.h	3.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 clk	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 clk-provider.h	34.29 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 clk.h	19.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clkdev.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clock_cooling.h	2.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clockchips.h	7.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocksource.h	8.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cm4000_cs.h	199 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cma.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmdline-parser.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cn_proc.h	1.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cnt32_to_63.h	3.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 coda.h	2.16 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 coda_psdev.h	2.98 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compaction.h	7.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	27.39 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compiler-clang.h	1.31 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compiler-gcc.h	12.6 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compiler-intel.h	1.3 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compiler.h	10.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compiler_types.h	7.5 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 completion.h	4.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 component.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 concap.h	3.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 configfs.h	9.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 connector.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 console.h	6.72 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 console_struct.h	6.87 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 consolemap.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 container.h	668 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 context_tracking.h	4.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 context_tracking_state.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cordic.h	1.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 coredump.h	783 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 coresight-pmu.h	1.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 coresight-stm.h	152 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 coresight.h	9.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 count_zeros.h	1.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cper.h	16.11 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpu.h	6.76 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpu_cooling.h	3.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu_pm.h	2.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu_rmap.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpufeature.h	1.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpufreq.h	27.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpuhotplug.h	12.05 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpuidle.h	8.68 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpumask.h	25.38 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpuset.h	7.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 crash_core.h	2.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 crash_dump.h	2.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc-ccitt.h	369 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc-itu-t.h	613 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc-t10dif.h	415 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc16.h	622 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc32.h	2.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc32c.h	293 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc4.h	192 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc7.h	316 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc8.h	3.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cred.h	12.23 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 crush	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 crypto.h	55.52 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cryptohash.h	319 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cs5535.h	6.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ctype.h	1.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cuda.h	501 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cyclades.h	10.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 davinci_emac.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dax.h	3.65 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dca.h	2.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcache.h	18.78 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dccp.h	10.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcookies.h	1.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug_locks.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debugfs.h	10.51 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 debugobjects.h	3.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 decompress	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 delay.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delayacct.h	5.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 delayed_call.h	709 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dell-led.h	128 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 devcoredump.h	2.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 devfreq-event.h	5.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 devfreq.h	12.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 devfreq_cooling.h	3.54 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 device-mapper.h	17.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 device.h	55.51 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 device_cgroup.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 devpts_fs.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 digsig.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dim.h	8.98 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dio.h	10.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dirent.h	216 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dlm.h	6.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dlm_plock.h	678 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dm-dirty-log.h	3.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dm-io.h	1.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dm-kcopyd.h	2.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dm-region-hash.h	3.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dm9000.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 dma	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 dma-buf.h	14.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-contiguous.h	4.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-debug.h	5.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-direction.h	338 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-fence-array.h	2.49 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dma-fence.h	17.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-iommu.h	3.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dma-mapping.h	24.61 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dma_remapping.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dmaengine.h	46.04 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dmapool.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dmar.h	7.94 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dmi.h	4.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dnotify.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dns_resolver.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dqblk_qtree.h	2.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dqblk_v1.h	327 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dqblk_v2.h	406 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 drbd.h	10.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 drbd_genl.h	21.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 drbd_genl_api.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 drbd_limits.h	7.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ds2782_battery.h	158 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 dsa	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 dtlk.h	3.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dw_apb_timer.h	1.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dynamic_debug.h	5.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dynamic_queue_limits.h	3.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 earlycpio.h	359 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ecryptfs.h	3.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 edac.h	20.26 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 edd.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 edma.h	807 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeprom_93cx6.h	2.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeprom_93xx46.h	879 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 efi-bgrt.h	644 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 efi.h	49.1 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 efs_vh.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eisa.h	2.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elevator.h	9.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf-fdpic.h	2.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf-randomize.h	583 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	1.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elfcore-compat.h	1.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elfcore.h	2.52 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 elfnote.h	3.54 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 enclosure.h	4.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 err.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 errno.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 errqueue.h	524 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 errseq.h	373 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 etherdevice.h	15.65 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ethtool.h	17.3 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 eventfd.h	2.36 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 eventpoll.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 evm.h	2.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 export.h	3.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exportfs.h	7.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ext2_fs.h	967 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	999 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 extcon	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 extcon-provider.h	4.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 extcon.h	10.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 f2fs_fs.h	17.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 f75375s.h	541 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 falloc.h	792 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fanotify.h	245 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fault-inject.h	1.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	28.74 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 fbcon.h	492 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 fcdevice.h	988 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fcntl.h	1.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fd.h	490 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fddidevice.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fdtable.h	3.28 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 fec.h	609 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 file.h	2.18 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 filter.h	27.5 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 fips.h	167 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 firewire.h	13.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 firmware	-	11/17/2022 06:42:17 AM	rwxr-xr-x
📄 firmware-map.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 firmware.h	2.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixp-arith.h	4.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flex_array.h	4.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flex_proportions.h	2.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fmc-sdb.h	1.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fmc.h	9.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 font.h	1.6 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 fpga	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 frame.h	813 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 freezer.h	8.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 frontswap.h	2.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs.h	110.54 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 fs_enet_pd.h	3.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs_pin.h	619 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs_stack.h	811 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs_struct.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs_uart_pd.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fscache-cache.h	18.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 fscache.h	27.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fscrypt.h	8.93 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 fscrypt_notsupp.h	4.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fscrypt_supp.h	6.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsi.h	2.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 fsl	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 fsl-diu-fb.h	4.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_devices.h	4.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_hypervisor.h	2.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_ifc.h	25.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 fsldma.h	398 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsnotify.h	7.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsnotify_backend.h	16.66 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ftrace.h	29.91 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ftrace_irq.h	823 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 fwnode.h	4.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gameport.h	5.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gcd.h	193 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 genalloc.h	5.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 genetlink.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 genhd.h	22.77 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 genl_magic_func.h	12.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 genl_magic_struct.h	7.66 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 getcpu.h	641 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 gfp.h	23.37 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 glob.h	256 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 goldfish.h	605 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 gpio	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 gpio-pxa.h	571 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 gpio.h	5.19 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 gpio_keys.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	1.95 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hash.h	3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hashtable.h	6.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hdlc.h	3.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hdlcdrv.h	6.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hdmi.h	9.36 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hid-debug.h	2.07 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hid-roccat.h	688 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hid-sensor-hub.h	9.25 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hid-sensor-ids.h	7.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hid.h	35.93 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hiddev.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hidraw.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	5.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highuid.h	3.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hil.h	18.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hil_mlc.h	5.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hippidevice.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hmm.h	18.19 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 host1x.h	9.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hp_sdc.h	14.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hpet.h	2.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hrtimer.h	14.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 hsi	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 htcpld.h	617 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 huge_mm.h	10.1 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hugetlb.h	16.71 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hugetlb_cgroup.h	2.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb_inline.h	374 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	3.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_random.h	2.03 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hwmon-sysfs.h	1.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwmon-vid.h	1.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwmon.h	12.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwspinlock.h	11.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hyperv.h	38.89 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hypervisor.h	400 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 i2c	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 i2c-algo-bit.h	2.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-algo-pca.h	2.89 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 i2c-algo-pcf.h	1.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-dev.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-gpio.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-mux-gpio.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-mux.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-ocores.h	757 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-omap.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-pca-platform.h	441 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-pnx.h	923 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-pxa.h	438 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-smbus.h	1.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-xiic.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c.h	30.91 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 i7300_idle.h	1.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8042.h	2.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8253.h	809 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 icmp.h	863 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 icmpv6.h	2.5 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ide.h	46.27 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 idr.h	7.82 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ieee80211.h	83.19 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ieee802154.h	11.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_arp.h	1.86 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 if_bridge.h	2.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_eql.h	1.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_ether.h	1.47 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 if_fddi.h	3.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_frad.h	2.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_link.h	554 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_ltalk.h	188 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_macvlan.h	2.2 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 if_phonet.h	319 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_pppol2tp.h	727 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_pppox.h	3.05 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 if_tap.h	2.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_team.h	7.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_tun.h	1.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_tunnel.h	409 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_vlan.h	19.2 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 igmp.h	4.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ihex.h	1.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 iio	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 ima.h	2.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 imx-media.h	811 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 in.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 in6.h	1.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 inet.h	2.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 inet_diag.h	2.42 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 inetdevice.h	8.25 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 init.h	9.1 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 init_ohci1394_dma.h	196 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 init_task.h	7.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 initrd.h	685 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 inotify.h	696 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 input	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 input-polldev.h	2.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 input.h	18.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 integrity.h	1.05 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 intel-iommu.h	16.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 intel-pti.h	1.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel-svm.h	4.96 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 interrupt.h	21.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 interval_tree.h	831 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 interval_tree_generic.h	8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-64-nonatomic-hi-lo.h	1.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-64-nonatomic-lo-hi.h	1.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-mapping.h	4.36 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 io.h	5.86 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ioc3.h	3.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ioc4.h	5.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 iocontext.h	4.76 KB	11/01/2022 04:52:05 PM	rw-r--r--
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📁 irqchip	-	11/17/2022 06:42:23 AM	rwxr-xr-x
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📄 irqdesc.h	8.15 KB	11/01/2022 04:52:05 PM	rw-r--r--
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📁 lockd	-	11/17/2022 06:42:23 AM	rwxr-xr-x
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📁 mailbox	-	11/17/2022 06:42:23 AM	rwxr-xr-x
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📄 mailbox_controller.h	5.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
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📄 max17040_battery.h	474 bytes	01/28/2018 09:20:33 PM	rw-r--r--
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📄 memory_hotplug.h	10.29 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mempolicy.h	7.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mempool.h	2.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 memremap.h	7.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 memstick.h	9.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 mfd	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 mic_bus.h	3.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 micrel_phy.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 microchipphy.h	2.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 migrate.h	10.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 migrate_mode.h	758 bytes	01/28/2018 09:20:33 PM	rw-r--r--
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📄 miscdevice.h	2.81 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 mlx4	-	11/17/2022 06:42:23 AM	rwxr-xr-x
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📄 mm-arch-hooks.h	679 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mm.h	85.89 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mm_inline.h	3.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mm_types.h	19.25 KB	11/01/2022 04:52:05 PM	rw-r--r--
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📄 mman.h	3.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 mmc	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 mmdebug.h	2.32 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmiotrace.h	3.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	378 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_notifier.h	15.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	39.66 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mnt_namespace.h	617 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 mod_devicetable.h	19.35 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 module.h	22.23 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 moduleloader.h	2.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 mount.h	3.45 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mpage.h	761 bytes	01/28/2018 09:20:33 PM	rw-r--r--
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📄 mpls_iptunnel.h	178 bytes	01/28/2018 09:20:33 PM	rw-r--r--
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📄 msi.h	11.79 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 mtd	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 mutex.h	6.91 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 mux	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 mv643xx.h	52.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mv643xx_eth.h	1.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 netdevice.h	140.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 netfilter	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 netfilter.h	11.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 netfilter_arp	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📁 netfilter_bridge	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 netfilter_bridge.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 netfilter_defs.h	239 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 netfilter_ingress.h	1.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 netfilter_ipv4	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 netfilter_ipv4.h	424 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 netfilter_ipv6	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 netfilter_ipv6.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 netlink.h	6.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 nfs_fs_i.h	308 bytes	01/28/2018 09:20:33 PM	rw-r--r--
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📄 nfs_iostat.h	4.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nfs_page.h	6.26 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 nfs_xdr.h	38.79 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 nfsacl.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nl802154.h	4.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nls.h	3.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nmi.h	6.56 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 node.h	3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nodemask.h	17.08 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 nospec.h	2.14 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 notifier.h	7.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ns_common.h	235 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nsc_gpio.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nsproxy.h	2.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ntb.h	46.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ntb_transport.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nubus.h	4.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 numa.h	292 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvme-fc-driver.h	38.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvme-fc.h	8.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvme-rdma.h	2.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvme.h	26.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvmem-consumer.h	4.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvmem-provider.h	1.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvram.h	495 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 of.h	40.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 of_address.h	4.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_device.h	3.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_dma.h	2.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_fdt.h	4.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_gpio.h	4.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_graph.h	3.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_iommu.h	1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_irq.h	3.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_mdio.h	2.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_net.h	708 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_pci.h	2.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_pdt.h	1.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_platform.h	4.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_reserved_mem.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 oid_registry.h	3.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 olpc-ec.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 omap-dma.h	10.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 omap-dmaengine.h	583 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 omap-gpmc.h	2.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 omap-iommu.h	520 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 omap-mailbox.h	777 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 omapfb.h	1.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 once.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 oom.h	3.15 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 openvswitch.h	844 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 oprofile.h	6.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 osq_lock.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 overflow.h	9.26 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 oxu210hp.h	197 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 padata.h	5.82 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page-flags-layout.h	2.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page-flags.h	23.91 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 page-isolation.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_counter.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_ext.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_idle.h	2.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_owner.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_ref.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pageblock-flags.h	3.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pagemap.h	19.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pagevec.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 parman.h	2.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 parport.h	17.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 parport_pc.h	6.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 parser.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pata_arasan_cf_data.h	1.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 patchkey.h	757 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 path.h	572 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pch_dma.h	999 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-acpi.h	3.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-aspm.h	882 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci-ats.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-dma-compat.h	4.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-dma.h	454 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-ecam.h	2.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-ep-cfs.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-epc.h	5.38 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci-epf.h	4.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	81.59 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci_hotplug.h	6.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_ids.h	120.12 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pcieport_if.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pda_power.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pe.h	15.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu-defs.h	18.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 percpu-refcount.h	9.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu-rwsem.h	4.09 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 percpu.h	5.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu_counter.h	4.26 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 percpu_ida.h	2.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 perf	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 perf_event.h	38.74 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 perf_regs.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 personality.h	393 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pfn.h	666 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pfn_t.h	3.23 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 phonet.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 phy	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 phy.h	31.11 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 phy_fixed.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 phy_led_triggers.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 phylink.h	5.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pid.h	5.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pid_namespace.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pim.h	2.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 pinctrl	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 pipe_fs_i.h	6.46 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pkeys.h	916 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pktcdvd.h	5.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pl320-ipc.h	758 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 platform_data	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 platform_device.h	12.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 plist.h	8.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm-trace.h	940 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm.h	34.21 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pm2301_charger.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm_clock.h	2.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm_domain.h	9.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm_opp.h	10.08 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pm_qos.h	8.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm_runtime.h	8.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm_wakeirq.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm_wakeup.h	6.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmbus.h	1.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmu.h	2.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pnfs_osd_xdr.h	9.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pnp.h	14.89 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 poison.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 poll.h	3.24 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 posix-clock.h	4.55 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 posix-timers.h	3.55 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 posix_acl.h	3.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 posix_acl_xattr.h	1.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 power	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 power_supply.h	13.41 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 powercap.h	12.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppp-comp.h	3.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppp_channel.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppp_defs.h	454 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pps-gpio.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pps_kernel.h	3.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pr.h	566 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 prandom.h	2.81 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 preempt.h	9.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prefetch.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prime_numbers.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 printk.h	15.24 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 proc_fs.h	3.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 proc_ns.h	2.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	2.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 profile.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 projid.h	2.34 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 property.h	9.79 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 psci.h	1.87 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pstore.h	7.58 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pstore_ram.h	2.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pti.h	240 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 ptp_classify.h	2.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptp_clock_kernel.h	8.56 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ptr_ring.h	16.29 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ptrace.h	14.57 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 purgatory.h	589 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pvclock_gtod.h	548 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pwm.h	16.8 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pwm_backlight.h	740 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pxa168_eth.h	728 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pxa2xx_ssp.h	9.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 qcom_scm.h	4.12 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 qed	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 qnx6_fs.h	3.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 quicklist.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 quota.h	18.87 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 quotaops.h	10.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 radix-tree.h	21.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 raid	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 raid_class.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ramfs.h	762 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 random.h	3.99 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 range.h	651 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ras.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ratelimit.h	2.81 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rational.h	639 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rbtree.h	5.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rbtree_augmented.h	8.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rbtree_latch.h	6.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rcu_node_tree.h	4.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rcu_segcblist.h	3.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rcu_sync.h	2.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rculist.h	23.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rculist_bl.h	4.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rculist_nulls.h	6.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rcupdate.h	32.58 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rcupdate_wait.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rcutiny.h	3.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rcutree.h	3.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rcuwait.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reboot-mode.h	600 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 reboot.h	2.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reciprocal_div.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 refcount.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 regmap.h	42.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 regset.h	15.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 regulator	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 relay.h	8.84 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 remoteproc	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 remoteproc.h	18.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reservation.h	8.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 reset	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 reset-controller.h	2.16 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 reset.h	13.69 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 resource.h	339 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 resource_ext.h	2.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 restart_block.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rfkill.h	9.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rhashtable.h	38.24 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ring_buffer.h	6.79 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rio.h	19.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rio_drv.h	14.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rio_ids.h	1.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rio_regs.h	19.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rmap.h	8.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rmi.h	12.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rndis.h	16.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rodata_test.h	559 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 root_dev.h	579 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 rpmsg	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 rpmsg.h	8.37 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rslib.h	2.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 rtc	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 rtc.h	8.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rtmutex.h	3.47 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rtnetlink.h	4.27 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rtsx_common.h	1.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rtsx_pci.h	40.14 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rtsx_usb.h	15.95 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rwlock.h	4.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rwlock_api_smp.h	7.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rwlock_types.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rwsem-spinlock.h	1.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rwsem.h	6 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 s3c_adc_battery.h	971 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sa11x0-dma.h	572 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sbitmap.h	13.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scatterlist.h	13.29 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 scc.h	2.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 sched	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 sched.h	47.45 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sched_clock.h	661 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 scif.h	58.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scpi_protocol.h	2.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 screen_info.h	191 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sctp.h	21.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scx200.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scx200_gpio.h	2.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sdb.h	4.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sdla.h	6.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	2.66 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 securebits.h	239 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 security.h	47.81 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sed-opal.h	1.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 seg6_genl.h	136 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 seg6_hmac.h	136 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 seg6_iptunnel.h	148 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 seg6_local.h	100 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 selection.h	1.41 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 selinux.h	910 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sem.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 semaphore.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seq_buf.h	3.15 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 seq_file.h	6.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seq_file_net.h	713 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 seqlock.h	16.48 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 seqno-fence.h	3.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serdev.h	9.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	630 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial_8250.h	6.01 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 serial_bcm63xx.h	4.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial_core.h	17.19 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 serial_max3100.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial_pnx8xxx.h	2.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial_s3c.h	9.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial_sci.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serio.h	4.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 set_memory.h	740 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfi.h	5.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfi_acpi.h	3.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfp.h	10.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sh_clk.h	5.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sh_dma.h	3.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sh_eth.h	417 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sh_intc.h	3.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sh_timer.h	172 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shdma-base.h	4.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 shm.h	1.71 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 shmem_fs.h	5.33 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 shrinker.h	2.82 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 signal.h	12.57 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 signal_types.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 signalfd.h	817 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 siphash.h	5.59 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sirfsoc_dma.h	162 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sizes.h	1.26 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 skb_array.h	5.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 skbuff.h	120.16 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 slab.h	21.45 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 slab_def.h	2.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 slub_def.h	5.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sm501-regs.h	11.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sm501.h	4.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smc911x.h	294 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smc91x.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	5.67 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 smpboot.h	2.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 smsc911x.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smscphy.h	1.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 soc	-	11/17/2022 06:42:17 AM	rwxr-xr-x
📄 sock_diag.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 socket.h	11.35 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sonet.h	469 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sony-laptop.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sonypi.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sort.h	247 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sound.h	807 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 soundcard.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 spi	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 spinlock.h	11.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_api_smp.h	5.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_api_up.h	3.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types_up.h	726 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_up.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 splice.h	3.01 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 spmi.h	5.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sram.h	844 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 srcu.h	6.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 srcutiny.h	3.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 srcutree.h	5.15 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 ssb	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 ssbi.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackdepot.h	967 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackprotector.h	324 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	1.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 start_kernel.h	334 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stat.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 statfs.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 static_key.h	30 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stddef.h	620 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ste_modem_shm.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stm.h	4.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stmmac.h	5.39 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 stmp3xxx_rtc_wdt.h	332 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stmp_device.h	619 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stop_machine.h	4.68 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 string.h	14.97 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 string_helpers.h	2.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stringhash.h	2.65 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 stringify.h	341 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sudmac.h	1.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sungem_phy.h	3.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 sunrpc	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 sunserialcore.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sunxi-rsb.h	2.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 superhyway.h	2.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 suspend.h	19.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 svga.h	3.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 swait.h	9.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 swap.h	21.58 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 swap_cgroup.h	971 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 swap_slots.h	840 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 swapfile.h	556 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 swapops.h	9.27 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 swiotlb.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switchtec.h	8.1 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sxgbe_platform.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sync_file.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 synclink.h	989 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sys.h	960 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sys_soc.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscalls.h	39.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscore_ops.h	635 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysctl.h	7.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysfs.h	15.41 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 syslog.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysrq.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysv_fs.h	9.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 t10-pi.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 task_io_accounting.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 task_io_accounting_ops.h	2.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 task_work.h	617 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 taskstats_kern.h	957 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tboot.h	3.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tc.h	3.45 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tca6416_keypad.h	847 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tcp.h	15.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tee_drv.h	8.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 textsearch.h	4.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 textsearch_fsm.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tfrc.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thermal.h	19.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thinkpad_acpi.h	320 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	4.1 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 threads.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thunderbolt.h	19.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ti_wilink_st.h	14.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tick.h	7.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tifm.h	4.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timb_dma.h	1.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timb_gpio.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 time.h	3.71 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 time32.h	5.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 time64.h	4.01 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 timecounter.h	4.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timekeeper_internal.h	5.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timekeeping.h	5.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timekeeping32.h	3.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 timer.h	6.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timerfd.h	508 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 timeriomem-rng.h	475 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 timerqueue.h	1.18 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 timex.h	6.61 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tnum.h	2.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	4.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 torture.h	3.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 toshiba.h	904 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tpm.h	3 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tpm_command.h	847 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 trace.h	964 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 trace_clock.h	667 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 trace_events.h	16.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 trace_seq.h	3.74 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tracefs.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tracehook.h	7.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tracepoint-defs.h	778 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tracepoint.h	16.26 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 transport_class.h	2.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ts-nbus.h	532 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tsacct_kern.h	1.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tty.h	28.03 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tty_driver.h	15.45 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tty_flip.h	1.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tty_ldisc.h	7.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 typecheck.h	624 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	5.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 u64_stats_sync.h	5.43 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 uaccess.h	9.95 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ucb1400.h	4.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucs2_string.h	662 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 udp.h	3.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uidgid.h	4.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uio.h	7.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uio_driver.h	4.07 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 ulpi	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 umh.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 unaligned	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 uprobes.h	6.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 usb	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 usb.h	75.46 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 usb_usual.h	3.58 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 usbdevice_fs.h	2.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user-return-notifier.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	22 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user_namespace.h	4.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 userfaultfd_k.h	3.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 util_macros.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 utsname.h	1.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uuid.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 uwb	-	11/17/2022 06:42:23 AM	rwxr-xr-x
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Editing: rtsx_pci.h

/* Driver for Realtek PCI-Express card reader
 *
 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2, or (at your option) any
 * later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * Author:
 *   Wei WANG <wei_wang@realsil.com.cn>
 */

#ifndef __RTSX_PCI_H
#define __RTSX_PCI_H

#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/rtsx_common.h>

#define MAX_RW_REG_CNT			1024

#define RTSX_HCBAR			0x00
#define RTSX_HCBCTLR			0x04
#define   STOP_CMD			(0x01 << 28)
#define   READ_REG_CMD			0
#define   WRITE_REG_CMD			1
#define   CHECK_REG_CMD			2

#define RTSX_HDBAR			0x08
#define   SG_INT			0x04
#define   SG_END			0x02
#define   SG_VALID			0x01
#define   SG_NO_OP			0x00
#define   SG_TRANS_DATA			(0x02 << 4)
#define   SG_LINK_DESC			(0x03 << 4)
#define RTSX_HDBCTLR			0x0C
#define   SDMA_MODE			0x00
#define   ADMA_MODE			(0x02 << 26)
#define   STOP_DMA			(0x01 << 28)
#define   TRIG_DMA			(0x01 << 31)

#define RTSX_HAIMR			0x10
#define   HAIMR_TRANS_START		(0x01 << 31)
#define   HAIMR_READ			0x00
#define   HAIMR_WRITE			(0x01 << 30)
#define   HAIMR_READ_START		(HAIMR_TRANS_START | HAIMR_READ)
#define   HAIMR_WRITE_START		(HAIMR_TRANS_START | HAIMR_WRITE)
#define   HAIMR_TRANS_END			(HAIMR_TRANS_START)

#define RTSX_BIPR			0x14
#define   CMD_DONE_INT			(1 << 31)
#define   DATA_DONE_INT			(1 << 30)
#define   TRANS_OK_INT			(1 << 29)
#define   TRANS_FAIL_INT		(1 << 28)
#define   XD_INT			(1 << 27)
#define   MS_INT			(1 << 26)
#define   SD_INT			(1 << 25)
#define   GPIO0_INT			(1 << 24)
#define   OC_INT			(1 << 23)
#define   SD_WRITE_PROTECT		(1 << 19)
#define   XD_EXIST			(1 << 18)
#define   MS_EXIST			(1 << 17)
#define   SD_EXIST			(1 << 16)
#define   DELINK_INT			GPIO0_INT
#define   MS_OC_INT			(1 << 23)
#define   SD_OC_INT			(1 << 22)

#define RTSX_BIER			0x18
#define   CMD_DONE_INT_EN		(1 << 31)
#define   DATA_DONE_INT_EN		(1 << 30)
#define   TRANS_OK_INT_EN		(1 << 29)
#define   TRANS_FAIL_INT_EN		(1 << 28)
#define   XD_INT_EN			(1 << 27)
#define   MS_INT_EN			(1 << 26)
#define   SD_INT_EN			(1 << 25)
#define   GPIO0_INT_EN			(1 << 24)
#define   OC_INT_EN			(1 << 23)
#define   DELINK_INT_EN			GPIO0_INT_EN
#define   MS_OC_INT_EN			(1 << 23)
#define   SD_OC_INT_EN			(1 << 22)

/*
 * macros for easy use
 */
#define rtsx_pci_writel(pcr, reg, value) \
	iowrite32(value, (pcr)->remap_addr + reg)
#define rtsx_pci_readl(pcr, reg) \
	ioread32((pcr)->remap_addr + reg)
#define rtsx_pci_writew(pcr, reg, value) \
	iowrite16(value, (pcr)->remap_addr + reg)
#define rtsx_pci_readw(pcr, reg) \
	ioread16((pcr)->remap_addr + reg)
#define rtsx_pci_writeb(pcr, reg, value) \
	iowrite8(value, (pcr)->remap_addr + reg)
#define rtsx_pci_readb(pcr, reg) \
	ioread8((pcr)->remap_addr + reg)

#define rtsx_pci_read_config_byte(pcr, where, val) \
	pci_read_config_byte((pcr)->pci, where, val)

#define rtsx_pci_write_config_byte(pcr, where, val) \
	pci_write_config_byte((pcr)->pci, where, val)

#define rtsx_pci_read_config_dword(pcr, where, val) \
	pci_read_config_dword((pcr)->pci, where, val)

#define rtsx_pci_write_config_dword(pcr, where, val) \
	pci_write_config_dword((pcr)->pci, where, val)

#define STATE_TRANS_NONE		0
#define STATE_TRANS_CMD			1
#define STATE_TRANS_BUF			2
#define STATE_TRANS_SG			3

#define TRANS_NOT_READY			0
#define TRANS_RESULT_OK			1
#define TRANS_RESULT_FAIL		2
#define TRANS_NO_DEVICE			3

#define RTSX_RESV_BUF_LEN		4096
#define HOST_CMDS_BUF_LEN		1024
#define HOST_SG_TBL_BUF_LEN		(RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
#define HOST_SG_TBL_ITEMS		(HOST_SG_TBL_BUF_LEN / 8)
#define MAX_SG_ITEM_LEN			0x80000
#define HOST_TO_DEVICE			0
#define DEVICE_TO_HOST			1

#define OUTPUT_3V3			0
#define OUTPUT_1V8			1

#define RTSX_PHASE_MAX			32
#define RX_TUNING_CNT			3

#define MS_CFG				0xFD40
#define   SAMPLE_TIME_RISING		0x00
#define   SAMPLE_TIME_FALLING		0x80
#define   PUSH_TIME_DEFAULT		0x00
#define   PUSH_TIME_ODD			0x40
#define   NO_EXTEND_TOGGLE		0x00
#define   EXTEND_TOGGLE_CHK		0x20
#define   MS_BUS_WIDTH_1		0x00
#define   MS_BUS_WIDTH_4		0x10
#define   MS_BUS_WIDTH_8		0x18
#define   MS_2K_SECTOR_MODE		0x04
#define   MS_512_SECTOR_MODE		0x00
#define   MS_TOGGLE_TIMEOUT_EN		0x00
#define   MS_TOGGLE_TIMEOUT_DISEN	0x01
#define MS_NO_CHECK_INT			0x02
#define MS_TPC				0xFD41
#define MS_TRANS_CFG			0xFD42
#define   WAIT_INT			0x80
#define   NO_WAIT_INT			0x00
#define   NO_AUTO_READ_INT_REG		0x00
#define   AUTO_READ_INT_REG		0x40
#define   MS_CRC16_ERR			0x20
#define   MS_RDY_TIMEOUT		0x10
#define   MS_INT_CMDNK			0x08
#define   MS_INT_BREQ			0x04
#define   MS_INT_ERR			0x02
#define   MS_INT_CED			0x01
#define MS_TRANSFER			0xFD43
#define   MS_TRANSFER_START		0x80
#define   MS_TRANSFER_END		0x40
#define   MS_TRANSFER_ERR		0x20
#define   MS_BS_STATE			0x10
#define   MS_TM_READ_BYTES		0x00
#define   MS_TM_NORMAL_READ		0x01
#define   MS_TM_WRITE_BYTES		0x04
#define   MS_TM_NORMAL_WRITE		0x05
#define   MS_TM_AUTO_READ		0x08
#define   MS_TM_AUTO_WRITE		0x0C
#define MS_INT_REG			0xFD44
#define MS_BYTE_CNT			0xFD45
#define MS_SECTOR_CNT_L			0xFD46
#define MS_SECTOR_CNT_H			0xFD47
#define MS_DBUS_H			0xFD48

#define SD_CFG1				0xFDA0
#define   SD_CLK_DIVIDE_0		0x00
#define   SD_CLK_DIVIDE_256		0xC0
#define   SD_CLK_DIVIDE_128		0x80
#define   SD_BUS_WIDTH_1BIT		0x00
#define   SD_BUS_WIDTH_4BIT		0x01
#define   SD_BUS_WIDTH_8BIT		0x02
#define   SD_ASYNC_FIFO_NOT_RST		0x10
#define   SD_20_MODE			0x00
#define   SD_DDR_MODE			0x04
#define   SD_30_MODE			0x08
#define   SD_CLK_DIVIDE_MASK		0xC0
#define   SD_MODE_SELECT_MASK		0x0C
#define SD_CFG2				0xFDA1
#define   SD_CALCULATE_CRC7		0x00
#define   SD_NO_CALCULATE_CRC7		0x80
#define   SD_CHECK_CRC16		0x00
#define   SD_NO_CHECK_CRC16		0x40
#define   SD_NO_CHECK_WAIT_CRC_TO	0x20
#define   SD_WAIT_BUSY_END		0x08
#define   SD_NO_WAIT_BUSY_END		0x00
#define   SD_CHECK_CRC7			0x00
#define   SD_NO_CHECK_CRC7		0x04
#define   SD_RSP_LEN_0			0x00
#define   SD_RSP_LEN_6			0x01
#define   SD_RSP_LEN_17			0x02
#define   SD_RSP_TYPE_R0		0x04
#define   SD_RSP_TYPE_R1		0x01
#define   SD_RSP_TYPE_R1b		0x09
#define   SD_RSP_TYPE_R2		0x02
#define   SD_RSP_TYPE_R3		0x05
#define   SD_RSP_TYPE_R4		0x05
#define   SD_RSP_TYPE_R5		0x01
#define   SD_RSP_TYPE_R6		0x01
#define   SD_RSP_TYPE_R7		0x01
#define SD_CFG3				0xFDA2
#define   SD30_CLK_END_EN		0x10
#define   SD_RSP_80CLK_TIMEOUT_EN	0x01

#define SD_STAT1			0xFDA3
#define   SD_CRC7_ERR			0x80
#define   SD_CRC16_ERR			0x40
#define   SD_CRC_WRITE_ERR		0x20
#define   SD_CRC_WRITE_ERR_MASK		0x1C
#define   GET_CRC_TIME_OUT		0x02
#define   SD_TUNING_COMPARE_ERR		0x01
#define SD_STAT2			0xFDA4
#define   SD_RSP_80CLK_TIMEOUT		0x01

#define SD_BUS_STAT			0xFDA5
#define   SD_CLK_TOGGLE_EN		0x80
#define   SD_CLK_FORCE_STOP		0x40
#define   SD_DAT3_STATUS		0x10
#define   SD_DAT2_STATUS		0x08
#define   SD_DAT1_STATUS		0x04
#define   SD_DAT0_STATUS		0x02
#define   SD_CMD_STATUS			0x01
#define SD_PAD_CTL			0xFDA6
#define   SD_IO_USING_1V8		0x80
#define   SD_IO_USING_3V3		0x7F
#define   TYPE_A_DRIVING		0x00
#define   TYPE_B_DRIVING		0x01
#define   TYPE_C_DRIVING		0x02
#define   TYPE_D_DRIVING		0x03
#define SD_SAMPLE_POINT_CTL		0xFDA7
#define   DDR_FIX_RX_DAT		0x00
#define   DDR_VAR_RX_DAT		0x80
#define   DDR_FIX_RX_DAT_EDGE		0x00
#define   DDR_FIX_RX_DAT_14_DELAY	0x40
#define   DDR_FIX_RX_CMD		0x00
#define   DDR_VAR_RX_CMD		0x20
#define   DDR_FIX_RX_CMD_POS_EDGE	0x00
#define   DDR_FIX_RX_CMD_14_DELAY	0x10
#define   SD20_RX_POS_EDGE		0x00
#define   SD20_RX_14_DELAY		0x08
#define SD20_RX_SEL_MASK		0x08
#define SD_PUSH_POINT_CTL		0xFDA8
#define   DDR_FIX_TX_CMD_DAT		0x00
#define   DDR_VAR_TX_CMD_DAT		0x80
#define   DDR_FIX_TX_DAT_14_TSU		0x00
#define   DDR_FIX_TX_DAT_12_TSU		0x40
#define   DDR_FIX_TX_CMD_NEG_EDGE	0x00
#define   DDR_FIX_TX_CMD_14_AHEAD	0x20
#define   SD20_TX_NEG_EDGE		0x00
#define   SD20_TX_14_AHEAD		0x10
#define   SD20_TX_SEL_MASK		0x10
#define   DDR_VAR_SDCLK_POL_SWAP	0x01
#define SD_CMD0				0xFDA9
#define   SD_CMD_START			0x40
#define SD_CMD1				0xFDAA
#define SD_CMD2				0xFDAB
#define SD_CMD3				0xFDAC
#define SD_CMD4				0xFDAD
#define SD_CMD5				0xFDAE
#define SD_BYTE_CNT_L			0xFDAF
#define SD_BYTE_CNT_H			0xFDB0
#define SD_BLOCK_CNT_L			0xFDB1
#define SD_BLOCK_CNT_H			0xFDB2
#define SD_TRANSFER			0xFDB3
#define   SD_TRANSFER_START		0x80
#define   SD_TRANSFER_END		0x40
#define   SD_STAT_IDLE			0x20
#define   SD_TRANSFER_ERR		0x10
#define   SD_TM_NORMAL_WRITE		0x00
#define   SD_TM_AUTO_WRITE_3		0x01
#define   SD_TM_AUTO_WRITE_4		0x02
#define   SD_TM_AUTO_READ_3		0x05
#define   SD_TM_AUTO_READ_4		0x06
#define   SD_TM_CMD_RSP			0x08
#define   SD_TM_AUTO_WRITE_1		0x09
#define   SD_TM_AUTO_WRITE_2		0x0A
#define   SD_TM_NORMAL_READ		0x0C
#define   SD_TM_AUTO_READ_1		0x0D
#define   SD_TM_AUTO_READ_2		0x0E
#define   SD_TM_AUTO_TUNING		0x0F
#define SD_CMD_STATE			0xFDB5
#define   SD_CMD_IDLE			0x80

#define SD_DATA_STATE			0xFDB6
#define   SD_DATA_IDLE			0x80
#define REG_SD_STOP_SDCLK_CFG		0xFDB8
#define   SD30_CLK_STOP_CFG_EN		0x04
#define   SD30_CLK_STOP_CFG1		0x02
#define   SD30_CLK_STOP_CFG0		0x01
#define REG_PRE_RW_MODE			0xFD70
#define EN_INFINITE_MODE		0x01

#define SRCTL				0xFC13

#define DCM_DRP_CTL			0xFC23
#define   DCM_RESET			0x08
#define   DCM_LOCKED			0x04
#define   DCM_208M			0x00
#define   DCM_TX			0x01
#define   DCM_RX			0x02
#define DCM_DRP_TRIG			0xFC24
#define   DRP_START			0x80
#define   DRP_DONE			0x40
#define DCM_DRP_CFG			0xFC25
#define   DRP_WRITE			0x80
#define   DRP_READ			0x00
#define   DCM_WRITE_ADDRESS_50		0x50
#define   DCM_WRITE_ADDRESS_51		0x51
#define   DCM_READ_ADDRESS_00		0x00
#define   DCM_READ_ADDRESS_51		0x51
#define DCM_DRP_WR_DATA_L		0xFC26
#define DCM_DRP_WR_DATA_H		0xFC27
#define DCM_DRP_RD_DATA_L		0xFC28
#define DCM_DRP_RD_DATA_H		0xFC29
#define SD_VPCLK0_CTL			0xFC2A
#define SD_VPCLK1_CTL			0xFC2B
#define   PHASE_SELECT_MASK		0x1F
#define SD_DCMPS0_CTL			0xFC2C
#define SD_DCMPS1_CTL			0xFC2D
#define SD_VPTX_CTL			SD_VPCLK0_CTL
#define SD_VPRX_CTL			SD_VPCLK1_CTL
#define   PHASE_CHANGE			0x80
#define   PHASE_NOT_RESET		0x40
#define SD_DCMPS_TX_CTL			SD_DCMPS0_CTL
#define SD_DCMPS_RX_CTL			SD_DCMPS1_CTL
#define   DCMPS_CHANGE			0x80
#define   DCMPS_CHANGE_DONE		0x40
#define   DCMPS_ERROR			0x20
#define   DCMPS_CURRENT_PHASE		0x1F
#define CARD_CLK_SOURCE			0xFC2E
#define   CRC_FIX_CLK			(0x00 << 0)
#define   CRC_VAR_CLK0			(0x01 << 0)
#define   CRC_VAR_CLK1			(0x02 << 0)
#define   SD30_FIX_CLK			(0x00 << 2)
#define   SD30_VAR_CLK0			(0x01 << 2)
#define   SD30_VAR_CLK1			(0x02 << 2)
#define   SAMPLE_FIX_CLK		(0x00 << 4)
#define   SAMPLE_VAR_CLK0		(0x01 << 4)
#define   SAMPLE_VAR_CLK1		(0x02 << 4)
#define CARD_PWR_CTL			0xFD50
#define   PMOS_STRG_MASK		0x10
#define   PMOS_STRG_800mA		0x10
#define   PMOS_STRG_400mA		0x00
#define   SD_POWER_OFF			0x03
#define   SD_PARTIAL_POWER_ON		0x01
#define   SD_POWER_ON			0x00
#define   SD_POWER_MASK			0x03
#define   MS_POWER_OFF			0x0C
#define   MS_PARTIAL_POWER_ON		0x04
#define   MS_POWER_ON			0x00
#define   MS_POWER_MASK			0x0C
#define   BPP_POWER_OFF			0x0F
#define   BPP_POWER_5_PERCENT_ON	0x0E
#define   BPP_POWER_10_PERCENT_ON	0x0C
#define   BPP_POWER_15_PERCENT_ON	0x08
#define   BPP_POWER_ON			0x00
#define   BPP_POWER_MASK		0x0F
#define   SD_VCC_PARTIAL_POWER_ON	0x02
#define   SD_VCC_POWER_ON		0x00
#define CARD_CLK_SWITCH			0xFD51
#define RTL8411B_PACKAGE_MODE		0xFD51
#define CARD_SHARE_MODE			0xFD52
#define   CARD_SHARE_MASK		0x0F
#define   CARD_SHARE_MULTI_LUN		0x00
#define   CARD_SHARE_NORMAL		0x00
#define   CARD_SHARE_48_SD		0x04
#define   CARD_SHARE_48_MS		0x08
#define   CARD_SHARE_BAROSSA_SD		0x01
#define   CARD_SHARE_BAROSSA_MS		0x02
#define CARD_DRIVE_SEL			0xFD53
#define   MS_DRIVE_8mA			(0x01 << 6)
#define   MMC_DRIVE_8mA			(0x01 << 4)
#define   XD_DRIVE_8mA			(0x01 << 2)
#define   GPIO_DRIVE_8mA		0x01
#define RTS5209_CARD_DRIVE_DEFAULT	(MS_DRIVE_8mA | MMC_DRIVE_8mA |\
					XD_DRIVE_8mA | GPIO_DRIVE_8mA)
#define RTL8411_CARD_DRIVE_DEFAULT	(MS_DRIVE_8mA | MMC_DRIVE_8mA |\
					XD_DRIVE_8mA)
#define RTSX_CARD_DRIVE_DEFAULT		(MS_DRIVE_8mA | GPIO_DRIVE_8mA)

#define CARD_STOP			0xFD54
#define   SPI_STOP			0x01
#define   XD_STOP			0x02
#define   SD_STOP			0x04
#define   MS_STOP			0x08
#define   SPI_CLR_ERR			0x10
#define   XD_CLR_ERR			0x20
#define   SD_CLR_ERR			0x40
#define   MS_CLR_ERR			0x80
#define CARD_OE				0xFD55
#define   SD_OUTPUT_EN			0x04
#define   MS_OUTPUT_EN			0x08
#define CARD_AUTO_BLINK			0xFD56
#define CARD_GPIO_DIR			0xFD57
#define CARD_GPIO			0xFD58
#define CARD_DATA_SOURCE		0xFD5B
#define   PINGPONG_BUFFER		0x01
#define   RING_BUFFER			0x00
#define SD30_CLK_DRIVE_SEL		0xFD5A
#define   DRIVER_TYPE_A			0x05
#define   DRIVER_TYPE_B			0x03
#define   DRIVER_TYPE_C			0x02
#define   DRIVER_TYPE_D			0x01
#define CARD_SELECT			0xFD5C
#define   SD_MOD_SEL			2
#define   MS_MOD_SEL			3
#define SD30_DRIVE_SEL			0xFD5E
#define   CFG_DRIVER_TYPE_A		0x02
#define   CFG_DRIVER_TYPE_B		0x03
#define   CFG_DRIVER_TYPE_C		0x01
#define   CFG_DRIVER_TYPE_D		0x00
#define SD30_CMD_DRIVE_SEL		0xFD5E
#define SD30_DAT_DRIVE_SEL		0xFD5F
#define CARD_CLK_EN			0xFD69
#define   SD_CLK_EN			0x04
#define   MS_CLK_EN			0x08
#define   SD40_CLK_EN		0x10
#define SDIO_CTRL			0xFD6B
#define CD_PAD_CTL			0xFD73
#define   CD_DISABLE_MASK		0x07
#define   MS_CD_DISABLE			0x04
#define   SD_CD_DISABLE			0x02
#define   XD_CD_DISABLE			0x01
#define   CD_DISABLE			0x07
#define   CD_ENABLE			0x00
#define   MS_CD_EN_ONLY			0x03
#define   SD_CD_EN_ONLY			0x05
#define   XD_CD_EN_ONLY			0x06
#define   FORCE_CD_LOW_MASK		0x38
#define   FORCE_CD_XD_LOW		0x08
#define   FORCE_CD_SD_LOW		0x10
#define   FORCE_CD_MS_LOW		0x20
#define   CD_AUTO_DISABLE		0x40
#define FPDCTL				0xFC00
#define   SSC_POWER_DOWN		0x01
#define   SD_OC_POWER_DOWN		0x02
#define   ALL_POWER_DOWN		0x03
#define   OC_POWER_DOWN			0x02
#define PDINFO				0xFC01

#define CLK_CTL				0xFC02
#define   CHANGE_CLK			0x01
#define   CLK_LOW_FREQ			0x01

#define CLK_DIV				0xFC03
#define   CLK_DIV_1			0x01
#define   CLK_DIV_2			0x02
#define   CLK_DIV_4			0x03
#define   CLK_DIV_8			0x04
#define CLK_SEL				0xFC04

#define SSC_DIV_N_0			0xFC0F
#define SSC_DIV_N_1			0xFC10
#define SSC_CTL1			0xFC11
#define    SSC_RSTB			0x80
#define    SSC_8X_EN			0x40
#define    SSC_FIX_FRAC			0x20
#define    SSC_SEL_1M			0x00
#define    SSC_SEL_2M			0x08
#define    SSC_SEL_4M			0x10
#define    SSC_SEL_8M			0x18
#define SSC_CTL2			0xFC12
#define    SSC_DEPTH_MASK		0x07
#define    SSC_DEPTH_DISALBE		0x00
#define    SSC_DEPTH_4M			0x01
#define    SSC_DEPTH_2M			0x02
#define    SSC_DEPTH_1M			0x03
#define    SSC_DEPTH_500K		0x04
#define    SSC_DEPTH_250K		0x05
#define RCCTL				0xFC14

#define FPGA_PULL_CTL			0xFC1D
#define OLT_LED_CTL			0xFC1E
#define   LED_SHINE_MASK		0x08
#define   LED_SHINE_EN			0x08
#define   LED_SHINE_DISABLE		0x00
#define GPIO_CTL			0xFC1F

#define LDO_CTL				0xFC1E
#define   BPP_ASIC_1V7			0x00
#define   BPP_ASIC_1V8			0x01
#define   BPP_ASIC_1V9			0x02
#define   BPP_ASIC_2V0			0x03
#define   BPP_ASIC_2V7			0x04
#define   BPP_ASIC_2V8			0x05
#define   BPP_ASIC_3V2			0x06
#define   BPP_ASIC_3V3			0x07
#define   BPP_REG_TUNED18		0x07
#define   BPP_TUNED18_SHIFT_8402	5
#define   BPP_TUNED18_SHIFT_8411	4
#define   BPP_PAD_MASK			0x04
#define   BPP_PAD_3V3			0x04
#define   BPP_PAD_1V8			0x00
#define   BPP_LDO_POWB			0x03
#define   BPP_LDO_ON			0x00
#define   BPP_LDO_SUSPEND		0x02
#define   BPP_LDO_OFF			0x03
#define EFUSE_CTL			0xFC30
#define EFUSE_ADD			0xFC31
#define SYS_VER				0xFC32
#define EFUSE_DATAL			0xFC34
#define EFUSE_DATAH			0xFC35

#define CARD_PULL_CTL1			0xFD60
#define CARD_PULL_CTL2			0xFD61
#define CARD_PULL_CTL3			0xFD62
#define CARD_PULL_CTL4			0xFD63
#define CARD_PULL_CTL5			0xFD64
#define CARD_PULL_CTL6			0xFD65

/* PCI Express Related Registers */
#define IRQEN0				0xFE20
#define IRQSTAT0			0xFE21
#define    DMA_DONE_INT			0x80
#define    SUSPEND_INT			0x40
#define    LINK_RDY_INT			0x20
#define    LINK_DOWN_INT		0x10
#define IRQEN1				0xFE22
#define IRQSTAT1			0xFE23
#define TLPRIEN				0xFE24
#define TLPRISTAT			0xFE25
#define TLPTIEN				0xFE26
#define TLPTISTAT			0xFE27
#define DMATC0				0xFE28
#define DMATC1				0xFE29
#define DMATC2				0xFE2A
#define DMATC3				0xFE2B
#define DMACTL				0xFE2C
#define   DMA_RST			0x80
#define   DMA_BUSY			0x04
#define   DMA_DIR_TO_CARD		0x00
#define   DMA_DIR_FROM_CARD		0x02
#define   DMA_EN			0x01
#define   DMA_128			(0 << 4)
#define   DMA_256			(1 << 4)
#define   DMA_512			(2 << 4)
#define   DMA_1024			(3 << 4)
#define   DMA_PACK_SIZE_MASK		0x30
#define BCTL				0xFE2D
#define RBBC0				0xFE2E
#define RBBC1				0xFE2F
#define RBDAT				0xFE30
#define RBCTL				0xFE34
#define   U_AUTO_DMA_EN_MASK		0x20
#define   U_AUTO_DMA_DISABLE		0x00
#define   RB_FLUSH			0x80
#define CFGADDR0			0xFE35
#define CFGADDR1			0xFE36
#define CFGDATA0			0xFE37
#define CFGDATA1			0xFE38
#define CFGDATA2			0xFE39
#define CFGDATA3			0xFE3A
#define CFGRWCTL			0xFE3B
#define PHYRWCTL			0xFE3C
#define PHYDATA0			0xFE3D
#define PHYDATA1			0xFE3E
#define PHYADDR				0xFE3F
#define MSGRXDATA0			0xFE40
#define MSGRXDATA1			0xFE41
#define MSGRXDATA2			0xFE42
#define MSGRXDATA3			0xFE43
#define MSGTXDATA0			0xFE44
#define MSGTXDATA1			0xFE45
#define MSGTXDATA2			0xFE46
#define MSGTXDATA3			0xFE47
#define MSGTXCTL			0xFE48
#define LTR_CTL				0xFE4A
#define LTR_TX_EN_MASK		BIT(7)
#define LTR_TX_EN_1			BIT(7)
#define LTR_TX_EN_0			0
#define LTR_LATENCY_MODE_MASK		BIT(6)
#define LTR_LATENCY_MODE_HW		0
#define LTR_LATENCY_MODE_SW		BIT(6)
#define OBFF_CFG			0xFE4C
#define   OBFF_EN_MASK			0x03
#define   OBFF_DISABLE			0x00

#define CDRESUMECTL			0xFE52
#define WAKE_SEL_CTL			0xFE54
#define PCLK_CTL			0xFE55
#define   PCLK_MODE_SEL			0x20
#define PME_FORCE_CTL			0xFE56

#define ASPM_FORCE_CTL			0xFE57
#define   FORCE_ASPM_CTL0		0x10
#define   FORCE_ASPM_VAL_MASK		0x03
#define   FORCE_ASPM_L1_EN		0x02
#define   FORCE_ASPM_L0_EN		0x01
#define   FORCE_ASPM_NO_ASPM		0x00
#define PM_CLK_FORCE_CTL		0xFE58
#define   CLK_PM_EN			0x01
#define FUNC_FORCE_CTL			0xFE59
#define   FUNC_FORCE_UPME_XMT_DBG	0x02
#define PERST_GLITCH_WIDTH		0xFE5C
#define CHANGE_LINK_STATE		0xFE5B
#define RESET_LOAD_REG			0xFE5E
#define EFUSE_CONTENT			0xFE5F
#define HOST_SLEEP_STATE		0xFE60
#define   HOST_ENTER_S1			1
#define   HOST_ENTER_S3			2

#define SDIO_CFG			0xFE70
#define PM_EVENT_DEBUG			0xFE71
#define   PME_DEBUG_0			0x08
#define NFTS_TX_CTRL			0xFE72

#define PWR_GATE_CTRL			0xFE75
#define   PWR_GATE_EN			0x01
#define   LDO3318_PWR_MASK		0x06
#define   LDO_ON			0x00
#define   LDO_SUSPEND			0x04
#define   LDO_OFF			0x06
#define PWD_SUSPEND_EN			0xFE76
#define LDO_PWR_SEL			0xFE78

#define L1SUB_CONFIG1			0xFE8D
#define   AUX_CLK_ACTIVE_SEL_MASK	0x01
#define   MAC_CKSW_DONE			0x00
#define L1SUB_CONFIG2			0xFE8E
#define   L1SUB_AUTO_CFG		0x02
#define L1SUB_CONFIG3			0xFE8F
#define   L1OFF_MBIAS2_EN_5250		BIT(7)

#define DUMMY_REG_RESET_0		0xFE90
#define   IC_VERSION_MASK		0x0F

#define REG_VREF			0xFE97
#define   PWD_SUSPND_EN			0x10
#define RTS5260_DMA_RST_CTL_0		0xFEBF
#define   RTS5260_DMA_RST		0x80
#define   RTS5260_ADMA3_RST		0x40
#define AUTOLOAD_CFG_BASE		0xFF00
#define RELINK_TIME_MASK		0x01
#define PETXCFG				0xFF03
#define FORCE_CLKREQ_DELINK_MASK	BIT(7)
#define FORCE_CLKREQ_LOW	0x80
#define FORCE_CLKREQ_HIGH	0x00

#define PM_CTRL1			0xFF44
#define   CD_RESUME_EN_MASK		0xF0

#define PM_CTRL2			0xFF45
#define PM_CTRL3			0xFF46
#define   SDIO_SEND_PME_EN		0x80
#define   FORCE_RC_MODE_ON		0x40
#define   FORCE_RX50_LINK_ON		0x20
#define   D3_DELINK_MODE_EN		0x10
#define   USE_PESRTB_CTL_DELINK		0x08
#define   DELAY_PIN_WAKE		0x04
#define   RESET_PIN_WAKE		0x02
#define   PM_WAKE_EN			0x01
#define PM_CTRL4			0xFF47

/* Memory mapping */
#define SRAM_BASE			0xE600
#define RBUF_BASE			0xF400
#define PPBUF_BASE1			0xF800
#define PPBUF_BASE2			0xFA00
#define IMAGE_FLAG_ADDR0		0xCE80
#define IMAGE_FLAG_ADDR1		0xCE81

#define RREF_CFG			0xFF6C
#define   RREF_VBGSEL_MASK		0x38
#define   RREF_VBGSEL_1V25		0x28

#define OOBS_CONFIG			0xFF6E
#define   OOBS_AUTOK_DIS		0x80
#define   OOBS_VAL_MASK			0x1F

#define LDO_DV18_CFG			0xFF70
#define   LDO_DV18_SR_MASK		0xC0
#define   LDO_DV18_SR_DF		0x40
#define   DV331812_MASK			0x70
#define   DV331812_33			0x70
#define   DV331812_17			0x30

#define LDO_CONFIG2			0xFF71
#define   LDO_D3318_MASK		0x07
#define   LDO_D3318_33V			0x07
#define   LDO_D3318_18V			0x02
#define   DV331812_VDD1			0x04
#define   DV331812_POWERON		0x08
#define   DV331812_POWEROFF		0x00

#define LDO_VCC_CFG0			0xFF72
#define   LDO_VCC_LMTVTH_MASK		0x30
#define   LDO_VCC_LMTVTH_2A		0x10
/*RTS5260*/
#define   RTS5260_DVCC_TUNE_MASK	0x70
#define   RTS5260_DVCC_33		0x70

#define LDO_VCC_CFG1			0xFF73
#define   LDO_VCC_REF_TUNE_MASK		0x30
#define   LDO_VCC_REF_1V2		0x20
#define   LDO_VCC_TUNE_MASK		0x07
#define   LDO_VCC_1V8			0x04
#define   LDO_VCC_3V3			0x07
#define   LDO_VCC_LMT_EN		0x08
/*RTS5260*/
#define	  LDO_POW_SDVDD1_MASK		0x08
#define	  LDO_POW_SDVDD1_ON		0x08
#define	  LDO_POW_SDVDD1_OFF		0x00

#define LDO_VIO_CFG			0xFF75
#define   LDO_VIO_SR_MASK		0xC0
#define   LDO_VIO_SR_DF			0x40
#define   LDO_VIO_REF_TUNE_MASK		0x30
#define   LDO_VIO_REF_1V2		0x20
#define   LDO_VIO_TUNE_MASK		0x07
#define   LDO_VIO_1V7			0x03
#define   LDO_VIO_1V8			0x04
#define   LDO_VIO_3V3			0x07

#define LDO_DV12S_CFG			0xFF76
#define   LDO_REF12_TUNE_MASK		0x18
#define   LDO_REF12_TUNE_DF		0x10
#define   LDO_D12_TUNE_MASK		0x07
#define   LDO_D12_TUNE_DF		0x04

#define LDO_AV12S_CFG			0xFF77
#define   LDO_AV12S_TUNE_MASK		0x07
#define   LDO_AV12S_TUNE_DF		0x04

#define SD40_LDO_CTL1			0xFE7D
#define   SD40_VIO_TUNE_MASK		0x70
#define   SD40_VIO_TUNE_1V7		0x30
#define   SD_VIO_LDO_1V8		0x40
#define   SD_VIO_LDO_3V3		0x70

#define RTS5260_AUTOLOAD_CFG4		0xFF7F
#define   RTS5260_MIMO_DISABLE		0x8A

#define RTS5260_REG_GPIO_CTL0		0xFC1A
#define   RTS5260_REG_GPIO_MASK		0x01
#define   RTS5260_REG_GPIO_ON		0x01
#define   RTS5260_REG_GPIO_OFF		0x00

#define PWR_GLOBAL_CTRL			0xF200
#define PCIE_L1_2_EN			0x0C
#define PCIE_L1_1_EN			0x0A
#define PCIE_L1_0_EN			0x09
#define PWR_FE_CTL			0xF201
#define PCIE_L1_2_PD_FE_EN		0x0C
#define PCIE_L1_1_PD_FE_EN		0x0A
#define PCIE_L1_0_PD_FE_EN		0x09
#define CFG_PCIE_APHY_OFF_0		0xF204
#define CFG_PCIE_APHY_OFF_0_DEFAULT	0xBF
#define CFG_PCIE_APHY_OFF_1		0xF205
#define CFG_PCIE_APHY_OFF_1_DEFAULT	0xFF
#define CFG_PCIE_APHY_OFF_2		0xF206
#define CFG_PCIE_APHY_OFF_2_DEFAULT	0x01
#define CFG_PCIE_APHY_OFF_3		0xF207
#define CFG_PCIE_APHY_OFF_3_DEFAULT	0x00
#define CFG_L1_0_PCIE_MAC_RET_VALUE	0xF20C
#define CFG_L1_0_PCIE_DPHY_RET_VALUE	0xF20E
#define CFG_L1_0_SYS_RET_VALUE		0xF210
#define CFG_L1_0_CRC_MISC_RET_VALUE	0xF212
#define CFG_L1_0_CRC_SD30_RET_VALUE	0xF214
#define CFG_L1_0_CRC_SD40_RET_VALUE	0xF216
#define CFG_LP_FPWM_VALUE		0xF219
#define CFG_LP_FPWM_VALUE_DEFAULT	0x18
#define PWC_CDR				0xF253
#define PWC_CDR_DEFAULT			0x03
#define CFG_L1_0_RET_VALUE_DEFAULT	0x1B
#define CFG_L1_0_CRC_MISC_RET_VALUE_DEFAULT	0x0C

/* OCPCTL */
#define SD_DETECT_EN			0x08
#define SD_OCP_INT_EN			0x04
#define SD_OCP_INT_CLR			0x02
#define SD_OC_CLR			0x01

#define SDVIO_DETECT_EN			(1 << 7)
#define SDVIO_OCP_INT_EN		(1 << 6)
#define SDVIO_OCP_INT_CLR		(1 << 5)
#define SDVIO_OC_CLR			(1 << 4)

/* OCPSTAT */
#define SD_OCP_DETECT			0x08
#define SD_OC_NOW			0x04
#define SD_OC_EVER			0x02

#define SDVIO_OC_NOW			(1 << 6)
#define SDVIO_OC_EVER			(1 << 5)

#define REG_OCPCTL			0xFD6A
#define REG_OCPSTAT			0xFD6E
#define REG_OCPGLITCH			0xFD6C
#define REG_OCPPARA1			0xFD6B
#define REG_OCPPARA2			0xFD6D

/* rts5260 DV3318 OCP-related registers */
#define REG_DV3318_OCPCTL		0xFD89
#define DV3318_OCP_TIME_MASK	0xF0
#define DV3318_DETECT_EN		0x08
#define DV3318_OCP_INT_EN		0x04
#define DV3318_OCP_INT_CLR		0x02
#define DV3318_OCP_CLR			0x01

#define REG_DV3318_OCPSTAT		0xFD8A
#define DV3318_OCP_GlITCH_TIME_MASK	0xF0
#define DV3318_OCP_DETECT		0x08
#define DV3318_OCP_NOW			0x04
#define DV3318_OCP_EVER			0x02

#define SD_OCP_GLITCH_MASK		0x0F

/* OCPPARA1 */
#define SDVIO_OCP_TIME_60		0x00
#define SDVIO_OCP_TIME_100		0x10
#define SDVIO_OCP_TIME_200		0x20
#define SDVIO_OCP_TIME_400		0x30
#define SDVIO_OCP_TIME_600		0x40
#define SDVIO_OCP_TIME_800		0x50
#define SDVIO_OCP_TIME_1100		0x60
#define SDVIO_OCP_TIME_MASK		0x70

#define SD_OCP_TIME_60			0x00
#define SD_OCP_TIME_100			0x01
#define SD_OCP_TIME_200			0x02
#define SD_OCP_TIME_400			0x03
#define SD_OCP_TIME_600			0x04
#define SD_OCP_TIME_800			0x05
#define SD_OCP_TIME_1100		0x06
#define SD_OCP_TIME_MASK		0x07

/* OCPPARA2 */
#define SDVIO_OCP_THD_190		0x00
#define SDVIO_OCP_THD_250		0x10
#define SDVIO_OCP_THD_320		0x20
#define SDVIO_OCP_THD_380		0x30
#define SDVIO_OCP_THD_440		0x40
#define SDVIO_OCP_THD_500		0x50
#define SDVIO_OCP_THD_570		0x60
#define SDVIO_OCP_THD_630		0x70
#define SDVIO_OCP_THD_MASK		0x70

#define SD_OCP_THD_450			0x00
#define SD_OCP_THD_550			0x01
#define SD_OCP_THD_650			0x02
#define SD_OCP_THD_750			0x03
#define SD_OCP_THD_850			0x04
#define SD_OCP_THD_950			0x05
#define SD_OCP_THD_1050			0x06
#define SD_OCP_THD_1150			0x07
#define SD_OCP_THD_MASK			0x07

#define SDVIO_OCP_GLITCH_MASK		0xF0
#define SDVIO_OCP_GLITCH_NONE		0x00
#define SDVIO_OCP_GLITCH_50U		0x10
#define SDVIO_OCP_GLITCH_100U		0x20
#define SDVIO_OCP_GLITCH_200U		0x30
#define SDVIO_OCP_GLITCH_600U		0x40
#define SDVIO_OCP_GLITCH_800U		0x50
#define SDVIO_OCP_GLITCH_1M		0x60
#define SDVIO_OCP_GLITCH_2M		0x70
#define SDVIO_OCP_GLITCH_3M		0x80
#define SDVIO_OCP_GLITCH_4M		0x90
#define SDVIO_OCP_GLIVCH_5M		0xA0
#define SDVIO_OCP_GLITCH_6M		0xB0
#define SDVIO_OCP_GLITCH_7M		0xC0
#define SDVIO_OCP_GLITCH_8M		0xD0
#define SDVIO_OCP_GLITCH_9M		0xE0
#define SDVIO_OCP_GLITCH_10M		0xF0

#define SD_OCP_GLITCH_MASK		0x0F
#define SD_OCP_GLITCH_NONE		0x00
#define SD_OCP_GLITCH_50U		0x01
#define SD_OCP_GLITCH_100U		0x02
#define SD_OCP_GLITCH_200U		0x03
#define SD_OCP_GLITCH_600U		0x04
#define SD_OCP_GLITCH_800U		0x05
#define SD_OCP_GLITCH_1M		0x06
#define SD_OCP_GLITCH_2M		0x07
#define SD_OCP_GLITCH_3M		0x08
#define SD_OCP_GLITCH_4M		0x09
#define SD_OCP_GLIVCH_5M		0x0A
#define SD_OCP_GLITCH_6M		0x0B
#define SD_OCP_GLITCH_7M		0x0C
#define SD_OCP_GLITCH_8M		0x0D
#define SD_OCP_GLITCH_9M		0x0E
#define SD_OCP_GLITCH_10M		0x0F

/* Phy register */
#define PHY_PCR				0x00
#define   PHY_PCR_FORCE_CODE		0xB000
#define   PHY_PCR_OOBS_CALI_50		0x0800
#define   PHY_PCR_OOBS_VCM_08		0x0200
#define   PHY_PCR_OOBS_SEN_90		0x0040
#define   PHY_PCR_RSSI_EN		0x0002
#define   PHY_PCR_RX10K			0x0001

#define PHY_RCR0			0x01
#define PHY_RCR1			0x02
#define   PHY_RCR1_ADP_TIME_4		0x0400
#define   PHY_RCR1_VCO_COARSE		0x001F
#define   PHY_RCR1_INIT_27S		0x0A1F
#define PHY_SSCCR2			0x02
#define   PHY_SSCCR2_PLL_NCODE		0x0A00
#define   PHY_SSCCR2_TIME0		0x001C
#define   PHY_SSCCR2_TIME2_WIDTH	0x0003

#define PHY_RCR2			0x03
#define   PHY_RCR2_EMPHASE_EN		0x8000
#define   PHY_RCR2_NADJR		0x4000
#define   PHY_RCR2_CDR_SR_2		0x0100
#define   PHY_RCR2_FREQSEL_12		0x0040
#define   PHY_RCR2_CDR_SC_12P		0x0010
#define   PHY_RCR2_CALIB_LATE		0x0002
#define   PHY_RCR2_INIT_27S		0xC152
#define PHY_SSCCR3			0x03
#define   PHY_SSCCR3_STEP_IN		0x2740
#define   PHY_SSCCR3_CHECK_DELAY	0x0008
#define _PHY_ANA03			0x03
#define   _PHY_ANA03_TIMER_MAX		0x2700
#define   _PHY_ANA03_OOBS_DEB_EN	0x0040
#define   _PHY_CMU_DEBUG_EN		0x0008

#define PHY_RTCR			0x04
#define PHY_RDR				0x05
#define   PHY_RDR_RXDSEL_1_9		0x4000
#define   PHY_SSC_AUTO_PWD		0x0600
#define PHY_TCR0			0x06
#define PHY_TCR1			0x07
#define PHY_TUNE			0x08
#define   PHY_TUNE_TUNEREF_1_0		0x4000
#define   PHY_TUNE_VBGSEL_1252		0x0C00
#define   PHY_TUNE_SDBUS_33		0x0200
#define   PHY_TUNE_TUNED18		0x01C0
#define   PHY_TUNE_TUNED12		0X0020
#define   PHY_TUNE_TUNEA12		0x0004
#define   PHY_TUNE_VOLTAGE_MASK		0xFC3F
#define   PHY_TUNE_VOLTAGE_3V3		0x03C0
#define   PHY_TUNE_D18_1V8		0x0100
#define   PHY_TUNE_D18_1V7		0x0080
#define PHY_ANA08			0x08
#define   PHY_ANA08_RX_EQ_DCGAIN	0x5000
#define   PHY_ANA08_SEL_RX_EN		0x0400
#define   PHY_ANA08_RX_EQ_VAL		0x03C0
#define   PHY_ANA08_SCP			0x0020
#define   PHY_ANA08_SEL_IPI		0x0004

#define PHY_IMR				0x09
#define PHY_BPCR			0x0A
#define   PHY_BPCR_IBRXSEL		0x0400
#define   PHY_BPCR_IBTXSEL		0x0100
#define   PHY_BPCR_IB_FILTER		0x0080
#define   PHY_BPCR_CMIRROR_EN		0x0040

#define PHY_BIST			0x0B
#define PHY_RAW_L			0x0C
#define PHY_RAW_H			0x0D
#define PHY_RAW_DATA			0x0E
#define PHY_HOST_CLK_CTRL		0x0F
#define PHY_DMR				0x10
#define PHY_BACR			0x11
#define   PHY_BACR_BASIC_MASK		0xFFF3
#define PHY_IER				0x12
#define PHY_BCSR			0x13
#define PHY_BPR				0x14
#define PHY_BPNR2			0x15
#define PHY_BPNR			0x16
#define PHY_BRNR2			0x17
#define PHY_BENR			0x18
#define PHY_REV				0x19
#define   PHY_REV_RESV			0xE000
#define   PHY_REV_RXIDLE_LATCHED	0x1000
#define   PHY_REV_P1_EN			0x0800
#define   PHY_REV_RXIDLE_EN		0x0400
#define   PHY_REV_CLKREQ_TX_EN		0x0200
#define   PHY_REV_CLKREQ_RX_EN		0x0100
#define   PHY_REV_CLKREQ_DT_1_0		0x0040
#define   PHY_REV_STOP_CLKRD		0x0020
#define   PHY_REV_RX_PWST		0x0008
#define   PHY_REV_STOP_CLKWR		0x0004
#define _PHY_REV0			0x19
#define   _PHY_REV0_FILTER_OUT		0x3800
#define   _PHY_REV0_CDR_BYPASS_PFD	0x0100
#define   _PHY_REV0_CDR_RX_IDLE_BYPASS	0x0002

#define PHY_FLD0			0x1A
#define PHY_ANA1A			0x1A
#define   PHY_ANA1A_TXR_LOOPBACK	0x2000
#define   PHY_ANA1A_RXT_BIST		0x0500
#define   PHY_ANA1A_TXR_BIST		0x0040
#define   PHY_ANA1A_REV			0x0006
#define   PHY_FLD0_INIT_27S		0x2546
#define PHY_FLD1			0x1B
#define PHY_FLD2			0x1C
#define PHY_FLD3			0x1D
#define   PHY_FLD3_TIMER_4		0x0800
#define   PHY_FLD3_TIMER_6		0x0020
#define   PHY_FLD3_RXDELINK		0x0004
#define   PHY_FLD3_INIT_27S		0x0004
#define PHY_ANA1D			0x1D
#define   PHY_ANA1D_DEBUG_ADDR		0x0004
#define _PHY_FLD0			0x1D
#define   _PHY_FLD0_CLK_REQ_20C		0x8000
#define   _PHY_FLD0_RX_IDLE_EN		0x1000
#define   _PHY_FLD0_BIT_ERR_RSTN	0x0800
#define   _PHY_FLD0_BER_COUNT		0x01E0
#define   _PHY_FLD0_BER_TIMER		0x001E
#define   _PHY_FLD0_CHECK_EN		0x0001

#define PHY_FLD4			0x1E
#define   PHY_FLD4_FLDEN_SEL		0x4000
#define   PHY_FLD4_REQ_REF		0x2000
#define   PHY_FLD4_RXAMP_OFF		0x1000
#define   PHY_FLD4_REQ_ADDA		0x0800
#define   PHY_FLD4_BER_COUNT		0x00E0
#define   PHY_FLD4_BER_TIMER		0x000A
#define   PHY_FLD4_BER_CHK_EN		0x0001
#define   PHY_FLD4_INIT_27S		0x5C7F
#define PHY_DIG1E			0x1E
#define   PHY_DIG1E_REV			0x4000
#define   PHY_DIG1E_D0_X_D1		0x1000
#define   PHY_DIG1E_RX_ON_HOST		0x0800
#define   PHY_DIG1E_RCLK_REF_HOST	0x0400
#define   PHY_DIG1E_RCLK_TX_EN_KEEP	0x0040
#define   PHY_DIG1E_RCLK_TX_TERM_KEEP	0x0020
#define   PHY_DIG1E_RCLK_RX_EIDLE_ON	0x0010
#define   PHY_DIG1E_TX_TERM_KEEP	0x0008
#define   PHY_DIG1E_RX_TERM_KEEP	0x0004
#define   PHY_DIG1E_TX_EN_KEEP		0x0002
#define   PHY_DIG1E_RX_EN_KEEP		0x0001
#define PHY_DUM_REG			0x1F

#define PCR_ASPM_SETTING_REG1		0x160
#define PCR_ASPM_SETTING_REG2		0x168
#define PCR_ASPM_SETTING_5260		0x178

#define PCR_SETTING_REG1		0x724
#define PCR_SETTING_REG2		0x814
#define PCR_SETTING_REG3		0x747

#define rtsx_pci_init_cmd(pcr)		((pcr)->ci = 0)

#define RTS5227_DEVICE_ID		0x5227
#define RTS_MAX_TIMES_FREQ_REDUCTION	8

struct rtsx_pcr;

struct pcr_handle {
	struct rtsx_pcr			*pcr;
};

struct pcr_ops {
	int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
	int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
	int		(*extra_init_hw)(struct rtsx_pcr *pcr);
	int		(*optimize_phy)(struct rtsx_pcr *pcr);
	int		(*turn_on_led)(struct rtsx_pcr *pcr);
	int		(*turn_off_led)(struct rtsx_pcr *pcr);
	int		(*enable_auto_blink)(struct rtsx_pcr *pcr);
	int		(*disable_auto_blink)(struct rtsx_pcr *pcr);
	int		(*card_power_on)(struct rtsx_pcr *pcr, int card);
	int		(*card_power_off)(struct rtsx_pcr *pcr, int card);
	int		(*switch_output_voltage)(struct rtsx_pcr *pcr,
						u8 voltage);
	unsigned int	(*cd_deglitch)(struct rtsx_pcr *pcr);
	int		(*conv_clk_and_div_n)(int clk, int dir);
	void		(*fetch_vendor_settings)(struct rtsx_pcr *pcr);
	void		(*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
	void		(*stop_cmd)(struct rtsx_pcr *pcr);

void (*set_aspm)(struct rtsx_pcr *pcr, bool enable);
	int (*set_ltr_latency)(struct rtsx_pcr *pcr, u32 latency);
	int (*set_l1off_sub)(struct rtsx_pcr *pcr, u8 val);
	void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active);
	void (*full_on)(struct rtsx_pcr *pcr);
	void (*power_saving)(struct rtsx_pcr *pcr);
	void (*enable_ocp)(struct rtsx_pcr *pcr);
	void (*disable_ocp)(struct rtsx_pcr *pcr);
	void (*init_ocp)(struct rtsx_pcr *pcr);
	void (*process_ocp)(struct rtsx_pcr *pcr);
	int (*get_ocpstat)(struct rtsx_pcr *pcr, u8 *val);
	void (*clear_ocpstat)(struct rtsx_pcr *pcr);
};

enum PDEV_STAT  {PDEV_STAT_IDLE, PDEV_STAT_RUN};

#define ASPM_L1_1_EN_MASK		BIT(3)
#define ASPM_L1_2_EN_MASK		BIT(2)
#define PM_L1_1_EN_MASK		BIT(1)
#define PM_L1_2_EN_MASK		BIT(0)

#define ASPM_L1_1_EN			BIT(0)
#define ASPM_L1_2_EN			BIT(1)
#define PM_L1_1_EN				BIT(2)
#define PM_L1_2_EN				BIT(3)
#define LTR_L1SS_PWR_GATE_EN	BIT(4)
#define L1_SNOOZE_TEST_EN		BIT(5)
#define LTR_L1SS_PWR_GATE_CHECK_CARD_EN	BIT(6)

enum dev_aspm_mode {
	DEV_ASPM_DYNAMIC,
	DEV_ASPM_BACKDOOR,
	DEV_ASPM_STATIC,
	DEV_ASPM_DISABLE,
};

/*
 * struct rtsx_cr_option  - card reader option
 * @dev_flags: device flags
 * @force_clkreq_0: force clock request
 * @ltr_en: enable ltr mode flag
 * @ltr_enabled: ltr mode in configure space flag
 * @ltr_active: ltr mode status
 * @ltr_active_latency: ltr mode active latency
 * @ltr_idle_latency: ltr mode idle latency
 * @ltr_l1off_latency: ltr mode l1off latency
 * @dev_aspm_mode: device aspm mode
 * @l1_snooze_delay: l1 snooze delay
 * @ltr_l1off_sspwrgate: ltr l1off sspwrgate
 * @ltr_l1off_snooze_sspwrgate: ltr l1off snooze sspwrgate
 * @ocp_en: enable ocp flag
 * @sd_400mA_ocp_thd: 400mA ocp thd
 * @sd_800mA_ocp_thd: 800mA ocp thd
 */
struct rtsx_cr_option {
	u32 dev_flags;
	bool force_clkreq_0;
	bool ltr_en;
	bool ltr_enabled;
	bool ltr_active;
	u32 ltr_active_latency;
	u32 ltr_idle_latency;
	u32 ltr_l1off_latency;
	enum dev_aspm_mode dev_aspm_mode;
	u32 l1_snooze_delay;
	u8 ltr_l1off_sspwrgate;
	u8 ltr_l1off_snooze_sspwrgate;
	bool ocp_en;
	u8 sd_400mA_ocp_thd;
	u8 sd_800mA_ocp_thd;
};

/*
 * struct rtsx_hw_param  - card reader hardware param
 * @interrupt_en: indicate which interrutp enable
 * @ocp_glitch: ocp glitch time
 */
struct rtsx_hw_param {
	u32 interrupt_en;
	u8 ocp_glitch;
};

#define rtsx_set_dev_flag(cr, flag) \
	((cr)->option.dev_flags |= (flag))
#define rtsx_clear_dev_flag(cr, flag) \
	((cr)->option.dev_flags &= ~(flag))
#define rtsx_check_dev_flag(cr, flag) \
	((cr)->option.dev_flags & (flag))

struct rtsx_pcr {
	struct pci_dev			*pci;
	unsigned int			id;
	int				pcie_cap;
	struct rtsx_cr_option	option;
	struct rtsx_hw_param hw_param;

/* pci resources */
	unsigned long			addr;
	void __iomem			*remap_addr;
	int				irq;

/* host reserved buffer */
	void				*rtsx_resv_buf;
	dma_addr_t			rtsx_resv_buf_addr;

void				*host_cmds_ptr;
	dma_addr_t			host_cmds_addr;
	int				ci;

void				*host_sg_tbl_ptr;
	dma_addr_t			host_sg_tbl_addr;
	int				sgi;

u32				bier;
	char				trans_result;

unsigned int			card_inserted;
	unsigned int			card_removed;
	unsigned int			card_exist;

struct delayed_work		carddet_work;
	struct delayed_work		idle_work;

spinlock_t			lock;
	struct mutex			pcr_mutex;
	struct completion		*done;
	struct completion		*finish_me;

unsigned int			cur_clock;
	bool				remove_pci;
	bool				msi_en;

#define EXTRA_CAPS_SD_SDR50		(1 << 0)
#define EXTRA_CAPS_SD_SDR104		(1 << 1)
#define EXTRA_CAPS_SD_DDR50		(1 << 2)
#define EXTRA_CAPS_MMC_HSDDR		(1 << 3)
#define EXTRA_CAPS_MMC_HS200		(1 << 4)
#define EXTRA_CAPS_MMC_8BIT		(1 << 5)
	u32				extra_caps;

#define IC_VER_A			0
#define IC_VER_B			1
#define IC_VER_C			2
#define IC_VER_D			3
	u8				ic_version;

u8				sd30_drive_sel_1v8;
	u8				sd30_drive_sel_3v3;
	u8				card_drive_sel;
#define ASPM_L1_EN			0x02
	u8				aspm_en;
	bool				aspm_enabled;

#define PCR_MS_PMOS			(1 << 0)
#define PCR_REVERSE_SOCKET		(1 << 1)
	u32				flags;

u32				tx_initial_phase;
	u32				rx_initial_phase;

const u32			*sd_pull_ctl_enable_tbl;
	const u32			*sd_pull_ctl_disable_tbl;
	const u32			*ms_pull_ctl_enable_tbl;
	const u32			*ms_pull_ctl_disable_tbl;

const struct pcr_ops		*ops;
	enum PDEV_STAT			state;

u16				reg_pm_ctrl3;

int				num_slots;
	struct rtsx_slot		*slots;

u8				dma_error_count;
	u8			ocp_stat;
	u8			ocp_stat2;
};

#define PID_524A	0x524A
#define PID_5249	0x5249
#define PID_5250	0x5250
#define PID_525A	0x525A
#define PID_5260	0x5260

#define CHK_PCI_PID(pcr, pid)		((pcr)->pci->device == (pid))
#define PCI_VID(pcr)			((pcr)->pci->vendor)
#define PCI_PID(pcr)			((pcr)->pci->device)
#define is_version(pcr, pid, ver)				\
	(CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
#define pcr_dbg(pcr, fmt, arg...)				\
	dev_dbg(&(pcr)->pci->dev, fmt, ##arg)

#define SDR104_PHASE(val)		((val) & 0xFF)
#define SDR50_PHASE(val)		(((val) >> 8) & 0xFF)
#define DDR50_PHASE(val)		(((val) >> 16) & 0xFF)
#define SDR104_TX_PHASE(pcr)		SDR104_PHASE((pcr)->tx_initial_phase)
#define SDR50_TX_PHASE(pcr)		SDR50_PHASE((pcr)->tx_initial_phase)
#define DDR50_TX_PHASE(pcr)		DDR50_PHASE((pcr)->tx_initial_phase)
#define SDR104_RX_PHASE(pcr)		SDR104_PHASE((pcr)->rx_initial_phase)
#define SDR50_RX_PHASE(pcr)		SDR50_PHASE((pcr)->rx_initial_phase)
#define DDR50_RX_PHASE(pcr)		DDR50_PHASE((pcr)->rx_initial_phase)
#define SET_CLOCK_PHASE(sdr104, sdr50, ddr50)	\
				(((ddr50) << 16) | ((sdr50) << 8) | (sdr104))

void rtsx_pci_start_run(struct rtsx_pcr *pcr);
int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
		u8 cmd_type, u16 reg_addr, u8 mask, u8 data);
void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
		int num_sg, bool read, int timeout);
int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
		int num_sg, bool read);
void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
		int num_sg, bool read);
int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
		int count, bool read, int timeout);
int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
		u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card);
int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage);
unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);

static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)
{
	return (u8 *)(pcr->host_cmds_ptr);
}

static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr,
		u8 mask, u8 append)
{
	int err;
	u8 val;

err = pci_read_config_byte(pcr->pci, addr, &val);
	if (err < 0)
		return err;
	return pci_write_config_byte(pcr->pci, addr, (val & mask) | append);
}

static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)
{
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg,     0xFF, val >> 24);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8);
	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);
}

static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,
	u16 mask, u16 append)
{
	int err;
	u16 val;

err = rtsx_pci_read_phy_register(pcr, addr, &val);
	if (err < 0)
		return err;

return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);
}

#endif