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11/17/2022 06:42:16 AM
rwxr-xr-x
📄
Kbuild
491 bytes
11/01/2022 04:52:05 PM
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agp.h
434 bytes
01/28/2018 09:20:33 PM
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apb.h
1.06 KB
01/28/2018 09:20:33 PM
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asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
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asm-prototypes.h
727 bytes
01/28/2018 09:20:33 PM
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asm.h
1.08 KB
01/28/2018 09:20:33 PM
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asmmacro.h
1.16 KB
01/28/2018 09:20:33 PM
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atomic.h
219 bytes
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atomic_32.h
2.26 KB
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atomic_64.h
3.34 KB
11/01/2022 04:52:05 PM
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auxio.h
310 bytes
01/28/2018 09:20:33 PM
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auxio_32.h
2.55 KB
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auxio_64.h
3.18 KB
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backoff.h
2.7 KB
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barrier.h
223 bytes
01/28/2018 09:20:33 PM
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barrier_32.h
160 bytes
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barrier_64.h
1.96 KB
01/28/2018 09:20:33 PM
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bbc.h
9.76 KB
01/28/2018 09:20:33 PM
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bitext.h
631 bytes
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bitops.h
219 bytes
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bitops_32.h
2.79 KB
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bitops_64.h
1.64 KB
01/28/2018 09:20:33 PM
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btext.h
145 bytes
01/28/2018 09:20:33 PM
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bug.h
588 bytes
11/01/2022 04:52:05 PM
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bugs.h
404 bytes
01/28/2018 09:20:33 PM
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cache.h
649 bytes
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cacheflush.h
373 bytes
01/28/2018 09:20:33 PM
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cacheflush_32.h
1.97 KB
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cacheflush_64.h
2.56 KB
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cachetlb_32.h
882 bytes
01/28/2018 09:20:33 PM
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chafsr.h
9.48 KB
01/28/2018 09:20:33 PM
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checksum.h
227 bytes
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checksum_32.h
6.81 KB
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checksum_64.h
4.4 KB
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chmctrl.h
7.91 KB
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clock.h
231 bytes
01/28/2018 09:20:33 PM
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clocksource.h
407 bytes
01/28/2018 09:20:33 PM
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cmpxchg.h
223 bytes
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cmpxchg_32.h
2.4 KB
01/28/2018 09:20:33 PM
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cmpxchg_64.h
5.13 KB
11/01/2022 04:52:05 PM
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compat.h
6.45 KB
01/28/2018 09:20:33 PM
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compat_signal.h
565 bytes
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contregs.h
1.9 KB
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cpu_type.h
579 bytes
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cpudata.h
378 bytes
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cpudata_32.h
729 bytes
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cpudata_64.h
1.13 KB
11/01/2022 04:52:05 PM
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current.h
991 bytes
01/28/2018 09:20:33 PM
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dcr.h
728 bytes
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dcu.h
1.48 KB
01/28/2018 09:20:33 PM
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delay.h
215 bytes
01/28/2018 09:20:33 PM
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delay_32.h
907 bytes
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delay_64.h
403 bytes
01/28/2018 09:20:33 PM
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device.h
565 bytes
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dma-mapping.h
632 bytes
01/28/2018 09:20:33 PM
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dma.h
6.6 KB
01/28/2018 09:20:33 PM
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ebus_dma.h
1.07 KB
01/28/2018 09:20:33 PM
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ecc.h
4.34 KB
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eeprom.h
254 bytes
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elf.h
207 bytes
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elf_32.h
3.19 KB
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elf_64.h
6.47 KB
01/28/2018 09:20:33 PM
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estate.h
2.23 KB
01/28/2018 09:20:33 PM
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extable_64.h
727 bytes
01/28/2018 09:20:33 PM
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fb.h
680 bytes
01/28/2018 09:20:33 PM
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fbio.h
2.26 KB
01/28/2018 09:20:33 PM
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fhc.h
4.43 KB
01/28/2018 09:20:33 PM
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floppy.h
219 bytes
01/28/2018 09:20:33 PM
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floppy_32.h
9.74 KB
01/28/2018 09:20:33 PM
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floppy_64.h
18.83 KB
01/28/2018 09:20:33 PM
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fpumacro.h
710 bytes
01/28/2018 09:20:33 PM
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ftrace.h
800 bytes
01/28/2018 09:20:33 PM
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futex.h
215 bytes
01/28/2018 09:20:33 PM
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📄
futex_32.h
82 bytes
01/28/2018 09:20:33 PM
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futex_64.h
2.15 KB
01/28/2018 09:20:33 PM
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hardirq.h
223 bytes
01/28/2018 09:20:33 PM
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📄
hardirq_32.h
334 bytes
01/28/2018 09:20:33 PM
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hardirq_64.h
417 bytes
01/28/2018 09:20:33 PM
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head.h
211 bytes
01/28/2018 09:20:33 PM
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head_32.h
2.56 KB
01/28/2018 09:20:33 PM
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head_64.h
2.13 KB
01/28/2018 09:20:33 PM
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hibernate.h
421 bytes
01/28/2018 09:20:33 PM
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highmem.h
2.02 KB
01/28/2018 09:20:33 PM
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hugetlb.h
2.09 KB
01/28/2018 09:20:33 PM
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hvtramp.h
782 bytes
01/28/2018 09:20:33 PM
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hw_irq.h
88 bytes
01/28/2018 09:20:33 PM
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hypervisor.h
110.71 KB
01/28/2018 09:20:33 PM
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📄
ide.h
2.19 KB
01/28/2018 09:20:33 PM
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idprom.h
656 bytes
01/28/2018 09:20:33 PM
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intr_queue.h
794 bytes
01/28/2018 09:20:33 PM
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📄
io-unit.h
2.41 KB
01/28/2018 09:20:33 PM
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📄
io.h
620 bytes
01/28/2018 09:20:33 PM
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io_32.h
3.51 KB
01/28/2018 09:20:33 PM
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io_64.h
10.66 KB
11/01/2022 04:52:05 PM
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📄
ioctls.h
358 bytes
01/28/2018 09:20:33 PM
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iommu.h
215 bytes
01/28/2018 09:20:33 PM
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📄
iommu_32.h
5.73 KB
01/28/2018 09:20:33 PM
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iommu_64.h
2.43 KB
01/28/2018 09:20:33 PM
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📄
irq.h
207 bytes
01/28/2018 09:20:33 PM
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📄
irq_32.h
526 bytes
01/28/2018 09:20:33 PM
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irq_64.h
3.06 KB
01/28/2018 09:20:33 PM
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irqflags.h
227 bytes
01/28/2018 09:20:33 PM
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📄
irqflags_32.h
1.03 KB
01/28/2018 09:20:33 PM
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irqflags_64.h
1.91 KB
01/28/2018 09:20:33 PM
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jump_label.h
1.01 KB
01/28/2018 09:20:33 PM
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kdebug.h
219 bytes
01/28/2018 09:20:33 PM
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kdebug_32.h
1.99 KB
01/28/2018 09:20:33 PM
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kdebug_64.h
393 bytes
01/28/2018 09:20:33 PM
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📄
kgdb.h
1014 bytes
01/28/2018 09:20:33 PM
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kmap_types.h
233 bytes
01/28/2018 09:20:33 PM
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kprobes.h
1.41 KB
01/28/2018 09:20:33 PM
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ldc.h
4.37 KB
01/28/2018 09:20:33 PM
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leon.h
7.37 KB
01/28/2018 09:20:33 PM
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leon_amba.h
8.09 KB
01/28/2018 09:20:33 PM
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leon_pci.h
512 bytes
01/28/2018 09:20:33 PM
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lsu.h
1.04 KB
01/28/2018 09:20:33 PM
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📄
machines.h
1.5 KB
01/28/2018 09:20:33 PM
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mbus.h
2.93 KB
01/28/2018 09:20:33 PM
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mc146818rtc.h
298 bytes
01/28/2018 09:20:33 PM
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mc146818rtc_32.h
699 bytes
01/28/2018 09:20:33 PM
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mc146818rtc_64.h
689 bytes
01/28/2018 09:20:33 PM
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mdesc.h
2.99 KB
01/28/2018 09:20:33 PM
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memctrl.h
311 bytes
01/28/2018 09:20:33 PM
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mman.h
304 bytes
01/28/2018 09:20:33 PM
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mmu.h
207 bytes
01/28/2018 09:20:33 PM
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mmu_32.h
209 bytes
01/28/2018 09:20:33 PM
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mmu_64.h
3.14 KB
01/28/2018 09:20:33 PM
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📄
mmu_context.h
239 bytes
01/28/2018 09:20:33 PM
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mmu_context_32.h
1.07 KB
01/28/2018 09:20:33 PM
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mmu_context_64.h
4.15 KB
01/28/2018 09:20:33 PM
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mmzone.h
393 bytes
01/28/2018 09:20:33 PM
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msi.h
774 bytes
01/28/2018 09:20:33 PM
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mxcc.h
4.33 KB
01/28/2018 09:20:33 PM
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nmi.h
354 bytes
01/28/2018 09:20:33 PM
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ns87303.h
3.22 KB
01/28/2018 09:20:33 PM
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obio.h
6.26 KB
01/28/2018 09:20:33 PM
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openprom.h
7.3 KB
01/28/2018 09:20:33 PM
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oplib.h
215 bytes
01/28/2018 09:20:33 PM
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oplib_32.h
5.92 KB
01/28/2018 09:20:33 PM
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oplib_64.h
8.12 KB
01/28/2018 09:20:33 PM
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page.h
274 bytes
01/28/2018 09:20:33 PM
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page_32.h
3.91 KB
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page_64.h
4.49 KB
01/28/2018 09:20:33 PM
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parport.h
5.68 KB
11/01/2022 04:52:05 PM
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pbm.h
1.47 KB
01/28/2018 09:20:33 PM
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pci.h
207 bytes
01/28/2018 09:20:33 PM
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pci_32.h
1.09 KB
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pci_64.h
1.49 KB
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pcic.h
5.77 KB
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pcr.h
1.85 KB
01/28/2018 09:20:33 PM
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percpu.h
219 bytes
01/28/2018 09:20:33 PM
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percpu_32.h
168 bytes
01/28/2018 09:20:33 PM
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percpu_64.h
515 bytes
01/28/2018 09:20:33 PM
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perf_event.h
802 bytes
01/28/2018 09:20:33 PM
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pgalloc.h
223 bytes
01/28/2018 09:20:33 PM
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pgalloc_32.h
1.91 KB
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pgalloc_64.h
2.85 KB
01/28/2018 09:20:33 PM
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pgtable.h
223 bytes
01/28/2018 09:20:33 PM
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pgtable_32.h
11.35 KB
01/28/2018 09:20:33 PM
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pgtable_64.h
30.71 KB
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pgtsrmmu.h
6.05 KB
01/28/2018 09:20:33 PM
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pil.h
1.08 KB
01/28/2018 09:20:33 PM
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processor.h
231 bytes
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processor_32.h
3.13 KB
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processor_64.h
7.58 KB
01/28/2018 09:20:33 PM
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prom.h
2.02 KB
01/28/2018 09:20:33 PM
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psr.h
1.38 KB
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ptrace.h
4.19 KB
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qrwlock.h
205 bytes
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qspinlock.h
215 bytes
01/28/2018 09:20:33 PM
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ross.h
5.52 KB
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sbi.h
3.34 KB
01/28/2018 09:20:33 PM
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scratchpad.h
547 bytes
01/28/2018 09:20:33 PM
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seccomp.h
225 bytes
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sections.h
289 bytes
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setup.h
1.52 KB
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sfafsr.h
3.14 KB
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sfp-machine.h
239 bytes
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sfp-machine_32.h
6.79 KB
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sfp-machine_64.h
3.1 KB
01/28/2018 09:20:33 PM
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shmparam.h
227 bytes
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shmparam_32.h
253 bytes
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shmparam_64.h
306 bytes
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sigcontext.h
2.55 KB
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signal.h
835 bytes
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smp.h
207 bytes
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smp_32.h
3.29 KB
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smp_64.h
1.84 KB
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sparsemem.h
349 bytes
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spinlock.h
227 bytes
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spinlock_32.h
4.22 KB
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spinlock_64.h
409 bytes
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spinlock_types.h
549 bytes
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spitfire.h
9.73 KB
01/28/2018 09:20:33 PM
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stacktrace.h
166 bytes
01/28/2018 09:20:33 PM
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starfire.h
418 bytes
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string.h
1.13 KB
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string_32.h
405 bytes
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string_64.h
505 bytes
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sunbpp.h
3.27 KB
01/28/2018 09:20:33 PM
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swift.h
3.07 KB
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switch_to.h
231 bytes
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switch_to_32.h
3.53 KB
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switch_to_64.h
2.58 KB
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syscall.h
3.41 KB
01/28/2018 09:20:33 PM
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syscalls.h
307 bytes
01/28/2018 09:20:33 PM
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termbits.h
198 bytes
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termios.h
4.94 KB
01/28/2018 09:20:33 PM
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thread_info.h
239 bytes
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thread_info_32.h
3.66 KB
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thread_info_64.h
7.84 KB
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timer.h
215 bytes
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Editing: chmctrl.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _SPARC64_CHMCTRL_H #define _SPARC64_CHMCTRL_H /* Cheetah memory controller programmable registers. */ #define CHMCTRL_TCTRL1 0x00 /* Memory Timing Control I */ #define CHMCTRL_TCTRL2 0x08 /* Memory Timing Control II */ #define CHMCTRL_TCTRL3 0x38 /* Memory Timing Control III */ #define CHMCTRL_TCTRL4 0x40 /* Memory Timing Control IV */ #define CHMCTRL_DECODE1 0x10 /* Memory Address Decode I */ #define CHMCTRL_DECODE2 0x18 /* Memory Address Decode II */ #define CHMCTRL_DECODE3 0x20 /* Memory Address Decode III */ #define CHMCTRL_DECODE4 0x28 /* Memory Address Decode IV */ #define CHMCTRL_MACTRL 0x30 /* Memory Address Control */ /* Memory Timing Control I */ #define TCTRL1_SDRAMCTL_DLY 0xf000000000000000UL #define TCTRL1_SDRAMCTL_DLY_SHIFT 60 #define TCTRL1_SDRAMCLK_DLY 0x0e00000000000000UL #define TCTRL1_SDRAMCLK_DLY_SHIFT 57 #define TCTRL1_R 0x0100000000000000UL #define TCTRL1_R_SHIFT 56 #define TCTRL1_AUTORFR_CYCLE 0x00fe000000000000UL #define TCTRL1_AUTORFR_CYCLE_SHIFT 49 #define TCTRL1_RD_WAIT 0x0001f00000000000UL #define TCTRL1_RD_WAIT_SHIFT 44 #define TCTRL1_PC_CYCLE 0x00000fc000000000UL #define TCTRL1_PC_CYCLE_SHIFT 38 #define TCTRL1_WR_MORE_RAS_PW 0x0000003f00000000UL #define TCTRL1_WR_MORE_RAS_PW_SHIFT 32 #define TCTRL1_RD_MORE_RAW_PW 0x00000000fc000000UL #define TCTRL1_RD_MORE_RAS_PW_SHIFT 26 #define TCTRL1_ACT_WR_DLY 0x0000000003f00000UL #define TCTRL1_ACT_WR_DLY_SHIFT 20 #define TCTRL1_ACT_RD_DLY 0x00000000000fc000UL #define TCTRL1_ACT_RD_DLY_SHIFT 14 #define TCTRL1_BANK_PRESENT 0x0000000000003000UL #define TCTRL1_BANK_PRESENT_SHIFT 12 #define TCTRL1_RFR_INT 0x0000000000000ff8UL #define TCTRL1_RFR_INT_SHIFT 3 #define TCTRL1_SET_MODE_REG 0x0000000000000004UL #define TCTRL1_SET_MODE_REG_SHIFT 2 #define TCTRL1_RFR_ENABLE 0x0000000000000002UL #define TCTRL1_RFR_ENABLE_SHIFT 1 #define TCTRL1_PRECHG_ALL 0x0000000000000001UL #define TCTRL1_PRECHG_ALL_SHIFT 0 /* Memory Timing Control II */ #define TCTRL2_WR_MSEL_DLY 0xfc00000000000000UL #define TCTRL2_WR_MSEL_DLY_SHIFT 58 #define TCTRL2_RD_MSEL_DLY 0x03f0000000000000UL #define TCTRL2_RD_MSEL_DLY_SHIFT 52 #define TCTRL2_WRDATA_THLD 0x000c000000000000UL #define TCTRL2_WRDATA_THLD_SHIFT 50 #define TCTRL2_RDWR_RD_TI_DLY 0x0003f00000000000UL #define TCTRL2_RDWR_RD_TI_DLY_SHIFT 44 #define TCTRL2_AUTOPRECHG_ENBL 0x0000080000000000UL #define TCTRL2_AUTOPRECHG_ENBL_SHIFT 43 #define TCTRL2_RDWR_PI_MORE_DLY 0x000007c000000000UL #define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38 #define TCTRL2_RDWR_1_DLY 0x0000003f00000000UL #define TCTRL2_RDWR_1_DLY_SHIFT 32 #define TCTRL2_WRWR_PI_MORE_DLY 0x00000000f8000000UL #define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27 #define TCTRL2_WRWR_1_DLY 0x0000000007e00000UL #define TCTRL2_WRWR_1_DLY_SHIFT 21 #define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000UL #define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16 #define TCTRL2_R 0x0000000000008000UL #define TCTRL2_R_SHIFT 15 #define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fffUL #define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0 /* Memory Timing Control III */ #define TCTRL3_SDRAM_CTL_DLY 0xf000000000000000UL #define TCTRL3_SDRAM_CTL_DLY_SHIFT 60 #define TCTRL3_SDRAM_CLK_DLY 0x0e00000000000000UL #define TCTRL3_SDRAM_CLK_DLY_SHIFT 57 #define TCTRL3_R 0x0100000000000000UL #define TCTRL3_R_SHIFT 56 #define TCTRL3_AUTO_RFR_CYCLE 0x00fe000000000000UL #define TCTRL3_AUTO_RFR_CYCLE_SHIFT 49 #define TCTRL3_RD_WAIT 0x0001f00000000000UL #define TCTRL3_RD_WAIT_SHIFT 44 #define TCTRL3_PC_CYCLE 0x00000fc000000000UL #define TCTRL3_PC_CYCLE_SHIFT 38 #define TCTRL3_WR_MORE_RAW_PW 0x0000003f00000000UL #define TCTRL3_WR_MORE_RAW_PW_SHIFT 32 #define TCTRL3_RD_MORE_RAW_PW 0x00000000fc000000UL #define TCTRL3_RD_MORE_RAW_PW_SHIFT 26 #define TCTRL3_ACT_WR_DLY 0x0000000003f00000UL #define TCTRL3_ACT_WR_DLY_SHIFT 20 #define TCTRL3_ACT_RD_DLY 0x00000000000fc000UL #define TCTRL3_ACT_RD_DLY_SHIFT 14 #define TCTRL3_BANK_PRESENT 0x0000000000003000UL #define TCTRL3_BANK_PRESENT_SHIFT 12 #define TCTRL3_RFR_INT 0x0000000000000ff8UL #define TCTRL3_RFR_INT_SHIFT 3 #define TCTRL3_SET_MODE_REG 0x0000000000000004UL #define TCTRL3_SET_MODE_REG_SHIFT 2 #define TCTRL3_RFR_ENABLE 0x0000000000000002UL #define TCTRL3_RFR_ENABLE_SHIFT 1 #define TCTRL3_PRECHG_ALL 0x0000000000000001UL #define TCTRL3_PRECHG_ALL_SHIFT 0 /* Memory Timing Control IV */ #define TCTRL4_WR_MSEL_DLY 0xfc00000000000000UL #define TCTRL4_WR_MSEL_DLY_SHIFT 58 #define TCTRL4_RD_MSEL_DLY 0x03f0000000000000UL #define TCTRL4_RD_MSEL_DLY_SHIFT 52 #define TCTRL4_WRDATA_THLD 0x000c000000000000UL #define TCTRL4_WRDATA_THLD_SHIFT 50 #define TCTRL4_RDWR_RD_RI_DLY 0x0003f00000000000UL #define TCTRL4_RDWR_RD_RI_DLY_SHIFT 44 #define TCTRL4_AUTO_PRECHG_ENBL 0x0000080000000000UL #define TCTRL4_AUTO_PRECHG_ENBL_SHIFT 43 #define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000UL #define TCTRL4_RD_WR_PI_MORE_DLY_SHIFT 38 #define TCTRL4_RD_WR_TI_DLY 0x0000003f00000000UL #define TCTRL4_RD_WR_TI_DLY_SHIFT 32 #define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000UL #define TCTRL4_WR_WR_PI_MORE_DLY_SHIFT 27 #define TCTRL4_WR_WR_TI_DLY 0x0000000007e00000UL #define TCTRL4_WR_WR_TI_DLY_SHIFT 21 #define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f000UL0 #define TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT 16 #define TCTRL4_R 0x0000000000008000UL #define TCTRL4_R_SHIFT 15 #define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fffUL #define TCTRL4_SDRAM_MODE_REG_DATA_SHIFT 0 /* All 4 memory address decoding registers have the * same layout. */ #define MEM_DECODE_VALID 0x8000000000000000UL /* Valid */ #define MEM_DECODE_VALID_SHIFT 63 #define MEM_DECODE_UK 0x001ffe0000000000UL /* Upper mask */ #define MEM_DECODE_UK_SHIFT 41 #define MEM_DECODE_UM 0x0000001ffff00000UL /* Upper match */ #define MEM_DECODE_UM_SHIFT 20 #define MEM_DECODE_LK 0x000000000003c000UL /* Lower mask */ #define MEM_DECODE_LK_SHIFT 14 #define MEM_DECODE_LM 0x0000000000000f00UL /* Lower match */ #define MEM_DECODE_LM_SHIFT 8 #define PA_UPPER_BITS 0x000007fffc000000UL #define PA_UPPER_BITS_SHIFT 26 #define PA_LOWER_BITS 0x00000000000003c0UL #define PA_LOWER_BITS_SHIFT 6 #define MACTRL_R0 0x8000000000000000UL #define MACTRL_R0_SHIFT 63 #define MACTRL_ADDR_LE_PW 0x7000000000000000UL #define MACTRL_ADDR_LE_PW_SHIFT 60 #define MACTRL_CMD_PW 0x0f00000000000000UL #define MACTRL_CMD_PW_SHIFT 56 #define MACTRL_HALF_MODE_WR_MSEL_DLY 0x00fc000000000000UL #define MACTRL_HALF_MODE_WR_MSEL_DLY_SHIFT 50 #define MACTRL_HALF_MODE_RD_MSEL_DLY 0x0003f00000000000UL #define MACTRL_HALF_MODE_RD_MSEL_DLY_SHIFT 44 #define MACTRL_HALF_MODE_SDRAM_CTL_DLY 0x00000f0000000000UL #define MACTRL_HALF_MODE_SDRAM_CTL_DLY_SHIFT 40 #define MACTRL_HALF_MODE_SDRAM_CLK_DLY 0x000000e000000000UL #define MACTRL_HALF_MODE_SDRAM_CLK_DLY_SHIFT 37 #define MACTRL_R1 0x0000001000000000UL #define MACTRL_R1_SHIFT 36 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000UL #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3_SHIFT 32 #define MACTRL_ENC_INTLV_B3 0x00000000f8000000UL #define MACTRL_ENC_INTLV_B3_SHIFT 27 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000UL #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2_SHIFT 23 #define MACTRL_ENC_INTLV_B2 0x00000000007c0000UL #define MACTRL_ENC_INTLV_B2_SHIFT 18 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000UL #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1_SHIFT 14 #define MACTRL_ENC_INTLV_B1 0x0000000000003e00UL #define MACTRL_ENC_INTLV_B1_SHIFT 9 #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0UL #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0_SHIFT 5 #define MACTRL_ENC_INTLV_B0 0x000000000000001fUL #define MACTRL_ENC_INTLV_B0_SHIFT 0 #endif /* _SPARC64_CHMCTRL_H */