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11/17/2022 06:42:16 AM
rwxr-xr-x
📄
Kbuild
491 bytes
11/01/2022 04:52:05 PM
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agp.h
434 bytes
01/28/2018 09:20:33 PM
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apb.h
1.06 KB
01/28/2018 09:20:33 PM
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asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
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asm-prototypes.h
727 bytes
01/28/2018 09:20:33 PM
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asm.h
1.08 KB
01/28/2018 09:20:33 PM
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asmmacro.h
1.16 KB
01/28/2018 09:20:33 PM
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atomic.h
219 bytes
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atomic_32.h
2.26 KB
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atomic_64.h
3.34 KB
11/01/2022 04:52:05 PM
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auxio.h
310 bytes
01/28/2018 09:20:33 PM
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auxio_32.h
2.55 KB
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auxio_64.h
3.18 KB
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backoff.h
2.7 KB
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barrier.h
223 bytes
01/28/2018 09:20:33 PM
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barrier_32.h
160 bytes
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barrier_64.h
1.96 KB
01/28/2018 09:20:33 PM
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bbc.h
9.76 KB
01/28/2018 09:20:33 PM
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bitext.h
631 bytes
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bitops.h
219 bytes
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bitops_32.h
2.79 KB
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bitops_64.h
1.64 KB
01/28/2018 09:20:33 PM
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btext.h
145 bytes
01/28/2018 09:20:33 PM
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bug.h
588 bytes
11/01/2022 04:52:05 PM
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bugs.h
404 bytes
01/28/2018 09:20:33 PM
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cache.h
649 bytes
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cacheflush.h
373 bytes
01/28/2018 09:20:33 PM
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cacheflush_32.h
1.97 KB
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cacheflush_64.h
2.56 KB
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cachetlb_32.h
882 bytes
01/28/2018 09:20:33 PM
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chafsr.h
9.48 KB
01/28/2018 09:20:33 PM
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checksum.h
227 bytes
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checksum_32.h
6.81 KB
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checksum_64.h
4.4 KB
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chmctrl.h
7.91 KB
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clock.h
231 bytes
01/28/2018 09:20:33 PM
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clocksource.h
407 bytes
01/28/2018 09:20:33 PM
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cmpxchg.h
223 bytes
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cmpxchg_32.h
2.4 KB
01/28/2018 09:20:33 PM
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cmpxchg_64.h
5.13 KB
11/01/2022 04:52:05 PM
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compat.h
6.45 KB
01/28/2018 09:20:33 PM
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compat_signal.h
565 bytes
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contregs.h
1.9 KB
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cpu_type.h
579 bytes
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cpudata.h
378 bytes
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cpudata_32.h
729 bytes
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cpudata_64.h
1.13 KB
11/01/2022 04:52:05 PM
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current.h
991 bytes
01/28/2018 09:20:33 PM
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dcr.h
728 bytes
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dcu.h
1.48 KB
01/28/2018 09:20:33 PM
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delay.h
215 bytes
01/28/2018 09:20:33 PM
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delay_32.h
907 bytes
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delay_64.h
403 bytes
01/28/2018 09:20:33 PM
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device.h
565 bytes
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dma-mapping.h
632 bytes
01/28/2018 09:20:33 PM
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dma.h
6.6 KB
01/28/2018 09:20:33 PM
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ebus_dma.h
1.07 KB
01/28/2018 09:20:33 PM
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ecc.h
4.34 KB
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eeprom.h
254 bytes
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elf.h
207 bytes
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elf_32.h
3.19 KB
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elf_64.h
6.47 KB
01/28/2018 09:20:33 PM
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estate.h
2.23 KB
01/28/2018 09:20:33 PM
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extable_64.h
727 bytes
01/28/2018 09:20:33 PM
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fb.h
680 bytes
01/28/2018 09:20:33 PM
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fbio.h
2.26 KB
01/28/2018 09:20:33 PM
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fhc.h
4.43 KB
01/28/2018 09:20:33 PM
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floppy.h
219 bytes
01/28/2018 09:20:33 PM
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floppy_32.h
9.74 KB
01/28/2018 09:20:33 PM
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floppy_64.h
18.83 KB
01/28/2018 09:20:33 PM
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fpumacro.h
710 bytes
01/28/2018 09:20:33 PM
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ftrace.h
800 bytes
01/28/2018 09:20:33 PM
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futex.h
215 bytes
01/28/2018 09:20:33 PM
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📄
futex_32.h
82 bytes
01/28/2018 09:20:33 PM
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futex_64.h
2.15 KB
01/28/2018 09:20:33 PM
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hardirq.h
223 bytes
01/28/2018 09:20:33 PM
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📄
hardirq_32.h
334 bytes
01/28/2018 09:20:33 PM
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hardirq_64.h
417 bytes
01/28/2018 09:20:33 PM
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head.h
211 bytes
01/28/2018 09:20:33 PM
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head_32.h
2.56 KB
01/28/2018 09:20:33 PM
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head_64.h
2.13 KB
01/28/2018 09:20:33 PM
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hibernate.h
421 bytes
01/28/2018 09:20:33 PM
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highmem.h
2.02 KB
01/28/2018 09:20:33 PM
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hugetlb.h
2.09 KB
01/28/2018 09:20:33 PM
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hvtramp.h
782 bytes
01/28/2018 09:20:33 PM
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hw_irq.h
88 bytes
01/28/2018 09:20:33 PM
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hypervisor.h
110.71 KB
01/28/2018 09:20:33 PM
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📄
ide.h
2.19 KB
01/28/2018 09:20:33 PM
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idprom.h
656 bytes
01/28/2018 09:20:33 PM
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intr_queue.h
794 bytes
01/28/2018 09:20:33 PM
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📄
io-unit.h
2.41 KB
01/28/2018 09:20:33 PM
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📄
io.h
620 bytes
01/28/2018 09:20:33 PM
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io_32.h
3.51 KB
01/28/2018 09:20:33 PM
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io_64.h
10.66 KB
11/01/2022 04:52:05 PM
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📄
ioctls.h
358 bytes
01/28/2018 09:20:33 PM
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iommu.h
215 bytes
01/28/2018 09:20:33 PM
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📄
iommu_32.h
5.73 KB
01/28/2018 09:20:33 PM
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iommu_64.h
2.43 KB
01/28/2018 09:20:33 PM
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📄
irq.h
207 bytes
01/28/2018 09:20:33 PM
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📄
irq_32.h
526 bytes
01/28/2018 09:20:33 PM
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irq_64.h
3.06 KB
01/28/2018 09:20:33 PM
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irqflags.h
227 bytes
01/28/2018 09:20:33 PM
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📄
irqflags_32.h
1.03 KB
01/28/2018 09:20:33 PM
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irqflags_64.h
1.91 KB
01/28/2018 09:20:33 PM
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jump_label.h
1.01 KB
01/28/2018 09:20:33 PM
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kdebug.h
219 bytes
01/28/2018 09:20:33 PM
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kdebug_32.h
1.99 KB
01/28/2018 09:20:33 PM
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kdebug_64.h
393 bytes
01/28/2018 09:20:33 PM
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📄
kgdb.h
1014 bytes
01/28/2018 09:20:33 PM
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kmap_types.h
233 bytes
01/28/2018 09:20:33 PM
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kprobes.h
1.41 KB
01/28/2018 09:20:33 PM
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ldc.h
4.37 KB
01/28/2018 09:20:33 PM
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leon.h
7.37 KB
01/28/2018 09:20:33 PM
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leon_amba.h
8.09 KB
01/28/2018 09:20:33 PM
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leon_pci.h
512 bytes
01/28/2018 09:20:33 PM
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lsu.h
1.04 KB
01/28/2018 09:20:33 PM
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📄
machines.h
1.5 KB
01/28/2018 09:20:33 PM
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mbus.h
2.93 KB
01/28/2018 09:20:33 PM
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mc146818rtc.h
298 bytes
01/28/2018 09:20:33 PM
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mc146818rtc_32.h
699 bytes
01/28/2018 09:20:33 PM
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mc146818rtc_64.h
689 bytes
01/28/2018 09:20:33 PM
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mdesc.h
2.99 KB
01/28/2018 09:20:33 PM
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memctrl.h
311 bytes
01/28/2018 09:20:33 PM
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mman.h
304 bytes
01/28/2018 09:20:33 PM
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mmu.h
207 bytes
01/28/2018 09:20:33 PM
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mmu_32.h
209 bytes
01/28/2018 09:20:33 PM
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mmu_64.h
3.14 KB
01/28/2018 09:20:33 PM
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📄
mmu_context.h
239 bytes
01/28/2018 09:20:33 PM
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mmu_context_32.h
1.07 KB
01/28/2018 09:20:33 PM
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mmu_context_64.h
4.15 KB
01/28/2018 09:20:33 PM
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mmzone.h
393 bytes
01/28/2018 09:20:33 PM
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msi.h
774 bytes
01/28/2018 09:20:33 PM
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mxcc.h
4.33 KB
01/28/2018 09:20:33 PM
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nmi.h
354 bytes
01/28/2018 09:20:33 PM
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ns87303.h
3.22 KB
01/28/2018 09:20:33 PM
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obio.h
6.26 KB
01/28/2018 09:20:33 PM
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openprom.h
7.3 KB
01/28/2018 09:20:33 PM
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oplib.h
215 bytes
01/28/2018 09:20:33 PM
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oplib_32.h
5.92 KB
01/28/2018 09:20:33 PM
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oplib_64.h
8.12 KB
01/28/2018 09:20:33 PM
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page.h
274 bytes
01/28/2018 09:20:33 PM
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page_32.h
3.91 KB
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page_64.h
4.49 KB
01/28/2018 09:20:33 PM
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parport.h
5.68 KB
11/01/2022 04:52:05 PM
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pbm.h
1.47 KB
01/28/2018 09:20:33 PM
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pci.h
207 bytes
01/28/2018 09:20:33 PM
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pci_32.h
1.09 KB
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pci_64.h
1.49 KB
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pcic.h
5.77 KB
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pcr.h
1.85 KB
01/28/2018 09:20:33 PM
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percpu.h
219 bytes
01/28/2018 09:20:33 PM
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percpu_32.h
168 bytes
01/28/2018 09:20:33 PM
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percpu_64.h
515 bytes
01/28/2018 09:20:33 PM
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perf_event.h
802 bytes
01/28/2018 09:20:33 PM
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pgalloc.h
223 bytes
01/28/2018 09:20:33 PM
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pgalloc_32.h
1.91 KB
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pgalloc_64.h
2.85 KB
01/28/2018 09:20:33 PM
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pgtable.h
223 bytes
01/28/2018 09:20:33 PM
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pgtable_32.h
11.35 KB
01/28/2018 09:20:33 PM
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pgtable_64.h
30.71 KB
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pgtsrmmu.h
6.05 KB
01/28/2018 09:20:33 PM
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pil.h
1.08 KB
01/28/2018 09:20:33 PM
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processor.h
231 bytes
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processor_32.h
3.13 KB
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processor_64.h
7.58 KB
01/28/2018 09:20:33 PM
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prom.h
2.02 KB
01/28/2018 09:20:33 PM
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psr.h
1.38 KB
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ptrace.h
4.19 KB
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qrwlock.h
205 bytes
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qspinlock.h
215 bytes
01/28/2018 09:20:33 PM
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ross.h
5.52 KB
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sbi.h
3.34 KB
01/28/2018 09:20:33 PM
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scratchpad.h
547 bytes
01/28/2018 09:20:33 PM
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seccomp.h
225 bytes
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sections.h
289 bytes
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setup.h
1.52 KB
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sfafsr.h
3.14 KB
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sfp-machine.h
239 bytes
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sfp-machine_32.h
6.79 KB
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sfp-machine_64.h
3.1 KB
01/28/2018 09:20:33 PM
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shmparam.h
227 bytes
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shmparam_32.h
253 bytes
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shmparam_64.h
306 bytes
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sigcontext.h
2.55 KB
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signal.h
835 bytes
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smp.h
207 bytes
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smp_32.h
3.29 KB
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smp_64.h
1.84 KB
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sparsemem.h
349 bytes
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spinlock.h
227 bytes
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spinlock_32.h
4.22 KB
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spinlock_64.h
409 bytes
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spinlock_types.h
549 bytes
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spitfire.h
9.73 KB
01/28/2018 09:20:33 PM
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stacktrace.h
166 bytes
01/28/2018 09:20:33 PM
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starfire.h
418 bytes
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string.h
1.13 KB
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string_32.h
405 bytes
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string_64.h
505 bytes
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sunbpp.h
3.27 KB
01/28/2018 09:20:33 PM
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swift.h
3.07 KB
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switch_to.h
231 bytes
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switch_to_32.h
3.53 KB
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switch_to_64.h
2.58 KB
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syscall.h
3.41 KB
01/28/2018 09:20:33 PM
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syscalls.h
307 bytes
01/28/2018 09:20:33 PM
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termbits.h
198 bytes
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termios.h
4.94 KB
01/28/2018 09:20:33 PM
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thread_info.h
239 bytes
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thread_info_32.h
3.66 KB
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thread_info_64.h
7.84 KB
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timer.h
215 bytes
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Editing: chafsr.h
Close
/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _SPARC64_CHAFSR_H #define _SPARC64_CHAFSR_H /* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */ /* Comments indicate which processor variants on which the bit definition * is valid. Codes are: * ch --> cheetah * ch+ --> cheetah plus * jp --> jalapeno */ /* All bits of this register except M_SYNDROME and E_SYNDROME are * read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only. */ /* Software bit set by linux trap handlers to indicate that the trap was * signalled at %tl >= 1. */ #define CHAFSR_TL1 (1UL << 63UL) /* n/a */ /* Unmapped error from system bus for prefetch queue or * store queue read operation */ #define CHPAFSR_DTO (1UL << 59UL) /* ch+ */ /* Bus error from system bus for prefetch queue or store queue * read operation */ #define CHPAFSR_DBERR (1UL << 58UL) /* ch+ */ /* Hardware corrected E-cache Tag ECC error */ #define CHPAFSR_THCE (1UL << 57UL) /* ch+ */ /* System interface protocol error, hw timeout caused */ #define JPAFSR_JETO (1UL << 57UL) /* jp */ /* SW handled correctable E-cache Tag ECC error */ #define CHPAFSR_TSCE (1UL << 56UL) /* ch+ */ /* Parity error on system snoop results */ #define JPAFSR_SCE (1UL << 56UL) /* jp */ /* Uncorrectable E-cache Tag ECC error */ #define CHPAFSR_TUE (1UL << 55UL) /* ch+ */ /* System interface protocol error, illegal command detected */ #define JPAFSR_JEIC (1UL << 55UL) /* jp */ /* Uncorrectable system bus data ECC error due to prefetch * or store fill request */ #define CHPAFSR_DUE (1UL << 54UL) /* ch+ */ /* System interface protocol error, illegal ADTYPE detected */ #define JPAFSR_JEIT (1UL << 54UL) /* jp */ /* Multiple errors of the same type have occurred. This bit is set when * an uncorrectable error or a SW correctable error occurs and the status * bit to report that error is already set. When multiple errors of * different types are indicated by setting multiple status bits. * * This bit is not set if multiple HW corrected errors with the same * status bit occur, only uncorrectable and SW correctable ones have * this behavior. * * This bit is not set when multiple ECC errors happen within a single * 64-byte system bus transaction. Only the first ECC error in a 16-byte * subunit will be logged. All errors in subsequent 16-byte subunits * from the same 64-byte transaction are ignored. */ #define CHAFSR_ME (1UL << 53UL) /* ch,ch+,jp */ /* Privileged state error has occurred. This is a capture of PSTATE.PRIV * at the time the error is detected. */ #define CHAFSR_PRIV (1UL << 52UL) /* ch,ch+,jp */ /* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error * bits and record the most recently detected errors. Bits accumulate * errors that have been detected since the last write to clear the bit. */ /* System interface protocol error. The processor asserts its' ERROR * pin when this event occurs and it also logs a specific cause code * into a JTAG scannable flop. */ #define CHAFSR_PERR (1UL << 51UL) /* ch,ch+,jp */ /* Internal processor error. The processor asserts its' ERROR * pin when this event occurs and it also logs a specific cause code * into a JTAG scannable flop. */ #define CHAFSR_IERR (1UL << 50UL) /* ch,ch+,jp */ /* System request parity error on incoming address */ #define CHAFSR_ISAP (1UL << 49UL) /* ch,ch+,jp */ /* HW Corrected system bus MTAG ECC error */ #define CHAFSR_EMC (1UL << 48UL) /* ch,ch+ */ /* Parity error on L2 cache tag SRAM */ #define JPAFSR_ETP (1UL << 48UL) /* jp */ /* Uncorrectable system bus MTAG ECC error */ #define CHAFSR_EMU (1UL << 47UL) /* ch,ch+ */ /* Out of range memory error has occurred */ #define JPAFSR_OM (1UL << 47UL) /* jp */ /* HW Corrected system bus data ECC error for read of interrupt vector */ #define CHAFSR_IVC (1UL << 46UL) /* ch,ch+ */ /* Error due to unsupported store */ #define JPAFSR_UMS (1UL << 46UL) /* jp */ /* Uncorrectable system bus data ECC error for read of interrupt vector */ #define CHAFSR_IVU (1UL << 45UL) /* ch,ch+,jp */ /* Unmapped error from system bus */ #define CHAFSR_TO (1UL << 44UL) /* ch,ch+,jp */ /* Bus error response from system bus */ #define CHAFSR_BERR (1UL << 43UL) /* ch,ch+,jp */ /* SW Correctable E-cache ECC error for instruction fetch or data access * other than block load. */ #define CHAFSR_UCC (1UL << 42UL) /* ch,ch+,jp */ /* Uncorrectable E-cache ECC error for instruction fetch or data access * other than block load. */ #define CHAFSR_UCU (1UL << 41UL) /* ch,ch+,jp */ /* Copyout HW Corrected ECC error */ #define CHAFSR_CPC (1UL << 40UL) /* ch,ch+,jp */ /* Copyout Uncorrectable ECC error */ #define CHAFSR_CPU (1UL << 39UL) /* ch,ch+,jp */ /* HW Corrected ECC error from E-cache for writeback */ #define CHAFSR_WDC (1UL << 38UL) /* ch,ch+,jp */ /* Uncorrectable ECC error from E-cache for writeback */ #define CHAFSR_WDU (1UL << 37UL) /* ch,ch+,jp */ /* HW Corrected ECC error from E-cache for store merge or block load */ #define CHAFSR_EDC (1UL << 36UL) /* ch,ch+,jp */ /* Uncorrectable ECC error from E-cache for store merge or block load */ #define CHAFSR_EDU (1UL << 35UL) /* ch,ch+,jp */ /* Uncorrectable system bus data ECC error for read of memory or I/O */ #define CHAFSR_UE (1UL << 34UL) /* ch,ch+,jp */ /* HW Corrected system bus data ECC error for read of memory or I/O */ #define CHAFSR_CE (1UL << 33UL) /* ch,ch+,jp */ /* Uncorrectable ECC error from remote cache/memory */ #define JPAFSR_RUE (1UL << 32UL) /* jp */ /* Correctable ECC error from remote cache/memory */ #define JPAFSR_RCE (1UL << 31UL) /* jp */ /* JBUS parity error on returned read data */ #define JPAFSR_BP (1UL << 30UL) /* jp */ /* JBUS parity error on data for writeback or block store */ #define JPAFSR_WBP (1UL << 29UL) /* jp */ /* Foreign read to DRAM incurring correctable ECC error */ #define JPAFSR_FRC (1UL << 28UL) /* jp */ /* Foreign read to DRAM incurring uncorrectable ECC error */ #define JPAFSR_FRU (1UL << 27UL) /* jp */ #define CHAFSR_ERRORS (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \ CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \ CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \ CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \ CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE) #define CHPAFSR_ERRORS (CHPAFSR_DTO | CHPAFSR_DBERR | CHPAFSR_THCE | \ CHPAFSR_TSCE | CHPAFSR_TUE | CHPAFSR_DUE | \ CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \ CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \ CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \ CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \ CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE) #define JPAFSR_ERRORS (JPAFSR_JETO | JPAFSR_SCE | JPAFSR_JEIC | \ JPAFSR_JEIT | CHAFSR_PERR | CHAFSR_IERR | \ CHAFSR_ISAP | JPAFSR_ETP | JPAFSR_OM | \ JPAFSR_UMS | CHAFSR_IVU | CHAFSR_TO | \ CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | \ CHAFSR_CPC | CHAFSR_CPU | CHAFSR_WDC | \ CHAFSR_WDU | CHAFSR_EDC | CHAFSR_EDU | \ CHAFSR_UE | CHAFSR_CE | JPAFSR_RUE | \ JPAFSR_RCE | JPAFSR_BP | JPAFSR_WBP | \ JPAFSR_FRC | JPAFSR_FRU) /* Active JBUS request signal when error occurred */ #define JPAFSR_JBREQ (0x7UL << 24UL) /* jp */ #define JPAFSR_JBREQ_SHIFT 24UL /* L2 cache way information */ #define JPAFSR_ETW (0x3UL << 22UL) /* jp */ #define JPAFSR_ETW_SHIFT 22UL /* System bus MTAG ECC syndrome. This field captures the status of the * first occurrence of the highest-priority error according to the M_SYND * overwrite policy. After the AFSR sticky bit, corresponding to the error * for which the M_SYND is reported, is cleared, the contents of the M_SYND * field will be unchanged by will be unfrozen for further error capture. */ #define CHAFSR_M_SYNDROME (0xfUL << 16UL) /* ch,ch+,jp */ #define CHAFSR_M_SYNDROME_SHIFT 16UL /* Agenid Id of the foreign device causing the UE/CE errors */ #define JPAFSR_AID (0x1fUL << 9UL) /* jp */ #define JPAFSR_AID_SHIFT 9UL /* System bus or E-cache data ECC syndrome. This field captures the status * of the first occurrence of the highest-priority error according to the * E_SYND overwrite policy. After the AFSR sticky bit, corresponding to the * error for which the E_SYND is reported, is cleare, the contents of the E_SYND * field will be unchanged but will be unfrozen for further error capture. */ #define CHAFSR_E_SYNDROME (0x1ffUL << 0UL) /* ch,ch+,jp */ #define CHAFSR_E_SYNDROME_SHIFT 0UL /* The AFSR must be explicitly cleared by software, it is not cleared automatically * by a read. Writes to bits <51:33> with bits set will clear the corresponding * bits in the AFSR. Bits associated with disrupting traps must be cleared before * interrupts are re-enabled to prevent multiple traps for the same error. I.e. * PSTATE.IE and AFSR bits control delivery of disrupting traps. * * Since there is only one AFAR, when multiple events have been logged by the * bits in the AFSR, at most one of these events will have its status captured * in the AFAR. The highest priority of those event bits will get AFAR logging. * The AFAR will be unlocked and available to capture the address of another event * as soon as the one bit in AFSR that corresponds to the event logged in AFAR is * cleared. For example, if AFSR.CE is detected, then AFSR.UE (which overwrites * the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked * and ready for another event, even though AFSR.CE is still set. The same rules * also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR. */ #endif /* _SPARC64_CHAFSR_H */