OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:21 AM	rwxr-xr-x
📄 hash-4k.h	3.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hash-64k.h	7.25 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hash.h	6.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	2.02 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kup-radix.h	649 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmu-hash.h	24.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	4.66 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgalloc.h	6.12 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable-4k.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-64k.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	35.48 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 radix-4k.h	391 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 radix-64k.h	395 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 radix.h	8.92 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 slice.h	841 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlbflush-hash.h	2.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush-radix.h	2.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	3.06 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: hugetlb.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_POWERPC_BOOK3S_64_HUGETLB_H
#define _ASM_POWERPC_BOOK3S_64_HUGETLB_H
/*
 * For radix we want generic code to handle hugetlb. But then if we want
 * both hash and radix to be enabled together we need to workaround the
 * limitations.
 */
void radix__flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
void radix__local_flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
extern unsigned long
radix__hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
				unsigned long len, unsigned long pgoff,
				unsigned long flags);

static inline int hstate_get_psize(struct hstate *hstate)
{
	unsigned long shift;

shift = huge_page_shift(hstate);
	if (shift == mmu_psize_defs[MMU_PAGE_2M].shift)
		return MMU_PAGE_2M;
	else if (shift == mmu_psize_defs[MMU_PAGE_1G].shift)
		return MMU_PAGE_1G;
	else if (shift == mmu_psize_defs[MMU_PAGE_16M].shift)
		return MMU_PAGE_16M;
	else if (shift == mmu_psize_defs[MMU_PAGE_16G].shift)
		return MMU_PAGE_16G;
	else {
		WARN(1, "Wrong huge page shift\n");
		return mmu_virtual_psize;
	}
}

#define arch_make_huge_pte arch_make_huge_pte
static inline pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma,
				       struct page *page, int writable)
{
	unsigned long page_shift;

if (!cpu_has_feature(CPU_FTR_POWER9_DD1))
		return entry;

page_shift = huge_page_shift(hstate_vma(vma));
	/*
	 * We don't support 1G hugetlb pages yet.
	 */
	VM_WARN_ON(page_shift == mmu_psize_defs[MMU_PAGE_1G].shift);
	if (page_shift == mmu_psize_defs[MMU_PAGE_2M].shift)
		return __pte(pte_val(entry) | R_PAGE_LARGE);
	else
		return entry;
}

#ifdef CONFIG_ARCH_HAS_GIGANTIC_PAGE
static inline bool gigantic_page_supported(void)
{
	/*
	 * We used gigantic page reservation with hypervisor assist in some case.
	 * We cannot use runtime allocation of gigantic pages in those platforms
	 * This is hash translation mode LPARs.
	 */
	if (firmware_has_feature(FW_FEATURE_LPAR) && !radix_enabled())
		return false;

return true;
}
#endif

#endif