OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:20 AM	rwxr-xr-x
📄 cvmx-address.h	9.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-agl-defs.h	70.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-asm.h	5.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-asxx-defs.h	17.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-boot-vector.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-bootinfo.h	13.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cvmx-bootmem.h	14.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-ciu-defs.h	214.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-ciu2-defs.h	173.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-ciu3-defs.h	10.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-cmd-queue.h	18.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-config.h	6.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-coremask.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-dbg-defs.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-dpi-defs.h	27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-fau.h	18.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-fpa-defs.h	37.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-fpa.h	8.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-gmxx-defs.h	226.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-gpio-defs.h	13.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-helper-board.h	4.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-helper-errata.h	1.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-helper-jtag.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-helper-loop.h	1.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-helper-npi.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-helper-rgmii.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-helper-sgmii.h	3.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-helper-spi.h	2.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-helper-util.h	5.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-helper-xaui.h	3.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-helper.h	7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-iob-defs.h	35.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-ipd-defs.h	56.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-ipd.h	10.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-l2c-defs.h	7.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-l2c.h	11.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-l2d-defs.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-l2t-defs.h	5.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-led-defs.h	7.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-lmcx-defs.h	88.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-mio-defs.h	141.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-mixx-defs.h	14.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-npei-defs.h	94.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-npi-defs.h	67.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-packet.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-pci-defs.h	56.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-pciercx-defs.h	11.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-pcsx-defs.h	33.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-pcsxx-defs.h	25.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-pemx-defs.h	20.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-pescx-defs.h	15.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-pexp-defs.h	16.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-pip-defs.h	87.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-pip.h	16.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-pko-defs.h	73.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-pko.h	19.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cvmx-pow-defs.h	33.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-pow.h	63.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-rnm-defs.h	6.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-rst-defs.h	7.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-scratch.h	3.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-sli-defs.h	3.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-smix-defs.h	11.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-spi.h	8.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-spinlock.h	6.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-spxx-defs.h	12.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-sriox-defs.h	42.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-srxx-defs.h	4.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-stxx-defs.h	10.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-sysinfo.h	3.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-uctlx-defs.h	12.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx-wqe.h	17.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cvmx.h	13.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 octeon-feature.h	6.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 octeon-model.h	16.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 octeon.h	12.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-octeon.h	1.65 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: cvmx-config.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __CVMX_CONFIG_H__
#define __CVMX_CONFIG_H__

/************************* Config Specific Defines ************************/
#define CVMX_LLM_NUM_PORTS 1
#define CVMX_NULL_POINTER_PROTECT 1
#define CVMX_ENABLE_DEBUG_PRINTS 1
/* PKO queues per port for interface 0 (ports 0-15) */
#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1
/* PKO queues per port for interface 1 (ports 16-31) */
#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1
/* Limit on the number of PKO ports enabled for interface 0 */
#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
/* Limit on the number of PKO ports enabled for interface 1 */
#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
/* PKO queues per port for PCI (ports 32-35) */
#define CVMX_PKO_QUEUES_PER_PORT_PCI 1
/* PKO queues per port for Loop devices (ports 36-39) */
#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1

/************************* FPA allocation *********************************/
/* Pool sizes in bytes, must be multiple of a cache line */
#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE)
#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE)

/* Pools in use */
/* Packet buffers */
#define CVMX_FPA_PACKET_POOL		    (0)
#define CVMX_FPA_PACKET_POOL_SIZE	    CVMX_FPA_POOL_0_SIZE
/* Work queue entries */
#define CVMX_FPA_WQE_POOL		    (1)
#define CVMX_FPA_WQE_POOL_SIZE		    CVMX_FPA_POOL_1_SIZE
/* PKO queue command buffers */
#define CVMX_FPA_OUTPUT_BUFFER_POOL	    (2)
#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE    CVMX_FPA_POOL_2_SIZE

/*************************  FAU allocation ********************************/
/* The fetch and add registers are allocated here.  They are arranged
 * in order of descending size so that all alignment constraints are
 * automatically met.  The enums are linked so that the following enum
 * continues allocating where the previous one left off, so the
 * numbering within each enum always starts with zero.	The macros
 * take care of the address increment size, so the values entered
 * always increase by 1.  FAU registers are accessed with byte
 * addresses.
 */

#define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START)
typedef enum {
	CVMX_FAU_REG_64_START	= 0,
	CVMX_FAU_REG_64_END	= CVMX_FAU_REG_64_ADDR(0),
} cvmx_fau_reg_64_t;

#define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START)
typedef enum {
	CVMX_FAU_REG_32_START	= CVMX_FAU_REG_64_END,
	CVMX_FAU_REG_32_END	= CVMX_FAU_REG_32_ADDR(0),
} cvmx_fau_reg_32_t;

#define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START)
typedef enum {
	CVMX_FAU_REG_16_START	= CVMX_FAU_REG_32_END,
	CVMX_FAU_REG_16_END	= CVMX_FAU_REG_16_ADDR(0),
} cvmx_fau_reg_16_t;

#define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START)
typedef enum {
	CVMX_FAU_REG_8_START	= CVMX_FAU_REG_16_END,
	CVMX_FAU_REG_8_END	= CVMX_FAU_REG_8_ADDR(0),
} cvmx_fau_reg_8_t;

/*
 * The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first
 * available FAU address that is not allocated in cvmx-config.h. This
 * is 64 bit aligned.
 */
#define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL))
#define CVMX_FAU_REG_END (2048)

/********************** scratch memory allocation *************************/
/* Scratchpad memory allocation.  Note that these are byte memory
 * addresses.  Some uses of scratchpad (IOBDMA for example) require
 * the use of 8-byte aligned addresses, so proper alignment needs to
 * be taken into account.
 */
/* Generic scratch iobdma area */
#define CVMX_SCR_SCRATCH	       (0)
/* First location available after cvmx-config.h allocated region. */
#define CVMX_SCR_REG_AVAIL_BASE	       (8)

/*
 * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve
 * before the beginning of the packet. If necessary, override the
 * default here.  See the IPD section of the hardware manual for MBUFF
 * SKIP details.
 */
#define CVMX_HELPER_FIRST_MBUFF_SKIP 184

/*
 * CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve
 * in each chained packet element. If necessary, override the default
 * here.
 */
#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0

/*
 * CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is
 * enabled for all input ports. This controls if IPD sends
 * backpressure to all ports if Octeon's FPA pools don't have enough
 * packet or work queue entries. Even when this is off, it is still
 * possible to get backpressure from individual hardware ports. When
 * configuring backpressure, also check
 * CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override
 * the default here.
 */
#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1

/*
 * CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper
 * function. Once it is enabled the hardware starts accepting
 * packets. You might want to skip the IPD enable if configuration
 * changes are need from the default helper setup. If necessary,
 * override the default here.
 */
#define CVMX_HELPER_ENABLE_IPD 0

/*
 * CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns
 * to incoming packets.
 */
#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED

#define CVMX_ENABLE_PARAMETER_CHECKING 0

/*
 * The following select which fields are used by the PIP to generate
 * the tag on INPUT
 * 0: don't include
 * 1: include
 */
#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP	0
#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP	0
#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT	0
#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT	0
#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER	0
#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP	0
#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP	0
#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT	0
#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT	0
#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL	0
#define CVMX_HELPER_INPUT_TAG_INPUT_PORT	1

/* Select skip mode for input ports */
#define CVMX_HELPER_INPUT_PORT_SKIP_MODE	CVMX_PIP_PORT_CFG_MODE_SKIPL2

/*
 * Force backpressure to be disabled.  This overrides all other
 * backpressure configuration.
 */
#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0

#endif /* __CVMX_CONFIG_H__ */