OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:15 AM	rwxr-xr-x
📄 Kbuild	886 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	5.27 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	6.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cache.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	2.55 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 delay.h	978 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	934 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	6.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu.h	90 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.25 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hexagon_vm.h	6.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intrinsics.h	1003 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	6.95 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 irq.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	871 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mem-layout.h	3.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	2.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	910 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	4.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	841 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	4.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	14.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	3.84 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 spinlock_types.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 suspend.h	872 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	1.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	4.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 time.h	980 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 timer-regs.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	3.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	941 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vm_fault.h	993 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vm_mmu.h	3.37 KB	01/28/2018 09:20:33 PM	rw-r--r--

Name

Size

Modified

Perms

📁 ..

11/17/2022 06:42:15 AM

rwxr-xr-x

📄 Kbuild

886 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 asm-offsets.h

35 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 atomic.h

5.27 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 bitops.h

6.62 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 cache.h

1.16 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cacheflush.h

3.8 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 checksum.h

1.61 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 cmpxchg.h

2.55 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 delay.h

978 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma-mapping.h

1.31 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 dma.h

934 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 elf.h

6.34 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 exec.h

1.01 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 fixmap.h

1.11 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 fpu.h

90 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 futex.h

2.25 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 hexagon_vm.h

6.39 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 intrinsics.h

1003 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 io.h

6.95 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 irq.h

1.13 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 irqflags.h

1.46 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 kgdb.h

1.36 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 linkage.h

871 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 mem-layout.h

3.42 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu.h

1.1 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 mmu_context.h

2.59 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 module.h

910 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 page.h

4.74 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 perf_event.h

841 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgalloc.h

4.08 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 pgtable.h

14.15 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 processor.h

3.8 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 smp.h

1.31 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 spinlock.h

3.84 KB

11/01/2022 04:52:05 PM

rw-r--r--

📄 spinlock_types.h

1.15 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 string.h

1.08 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 suspend.h

872 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 switch_to.h

1.09 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 syscall.h

1.38 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 thread_info.h

4.05 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 time.h

980 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 timer-regs.h

1.23 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 timex.h

1.13 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlb.h

1.21 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 tlbflush.h

2.08 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 traps.h

1.02 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 uaccess.h

3.67 KB

01/28/2018 09:20:33 PM

rw-r--r--

📄 vdso.h

941 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 vm_fault.h

993 bytes

01/28/2018 09:20:33 PM

rw-r--r--

📄 vm_mmu.h

3.37 KB

01/28/2018 09:20:33 PM

rw-r--r--

Editing: futex.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_HEXAGON_FUTEX_H
#define _ASM_HEXAGON_FUTEX_H

#ifdef __KERNEL__

#include <linux/futex.h>
#include <linux/uaccess.h>
#include <asm/errno.h>

/* XXX TODO-- need to add sync barriers! */

#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
	__asm__ __volatile( \
	"1: %0 = memw_locked(%3);\n" \
	    /* For example: %1 = %4 */ \
	    insn \
	"2: memw_locked(%3,p2) = %1;\n" \
	"   if (!p2) jump 1b;\n" \
	"   %1 = #0;\n" \
	"3:\n" \
	".section .fixup,\"ax\"\n" \
	"4: %1 = #%5;\n" \
	"   jump 3b\n" \
	".previous\n" \
	".section __ex_table,\"a\"\n" \
	".long 1b,4b,2b,4b\n" \
	".previous\n" \
	: "=&r" (oldval), "=&r" (ret), "+m" (*uaddr) \
	: "r" (uaddr), "r" (oparg), "i" (-EFAULT) \
	: "p2", "memory")

static inline int
arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr)
{
	int oldval = 0, ret;

pagefault_disable();

switch (op) {
	case FUTEX_OP_SET:
		__futex_atomic_op("%1 = %4\n", ret, oldval, uaddr, oparg);
		break;
	case FUTEX_OP_ADD:
		__futex_atomic_op("%1 = add(%0,%4)\n", ret, oldval, uaddr,
				  oparg);
		break;
	case FUTEX_OP_OR:
		__futex_atomic_op("%1 = or(%0,%4)\n", ret, oldval, uaddr,
				  oparg);
		break;
	case FUTEX_OP_ANDN:
		__futex_atomic_op("%1 = not(%4); %1 = and(%0,%1)\n", ret,
				  oldval, uaddr, oparg);
		break;
	case FUTEX_OP_XOR:
		__futex_atomic_op("%1 = xor(%0,%4)\n", ret, oldval, uaddr,
				  oparg);
		break;
	default:
		ret = -ENOSYS;
	}

pagefault_enable();

if (!ret)
		*oval = oldval;

return ret;
}

static inline int
futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 oldval,
			      u32 newval)
{
	int prev;
	int ret;

if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
		return -EFAULT;

__asm__ __volatile__ (
	"1: %1 = memw_locked(%3)\n"
	"   {\n"
	"      p2 = cmp.eq(%1,%4)\n"
	"      if (!p2.new) jump:NT 3f\n"
	"   }\n"
	"2: memw_locked(%3,p2) = %5\n"
	"   if (!p2) jump 1b\n"
	"3:\n"
	".section .fixup,\"ax\"\n"
	"4: %0 = #%6\n"
	"   jump 3b\n"
	".previous\n"
	".section __ex_table,\"a\"\n"
	".long 1b,4b,2b,4b\n"
	".previous\n"
	: "+r" (ret), "=&r" (prev), "+m" (*uaddr)
	: "r" (uaddr), "r" (oldval), "r" (newval), "i"(-EFAULT)
	: "p2", "memory");

*uval = prev;
	return ret;
}

#endif /* __KERNEL__ */
#endif /* _ASM_HEXAGON_FUTEX_H */