OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:15 AM	rwxr-xr-x
📄 Kbuild	886 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	5.27 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	6.62 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cache.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	2.55 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 delay.h	978 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	934 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	6.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpu.h	90 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.25 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 hexagon_vm.h	6.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intrinsics.h	1003 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	6.95 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 irq.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	871 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mem-layout.h	3.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	2.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	910 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	4.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	841 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	4.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	14.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	3.84 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 spinlock_types.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 suspend.h	872 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	1.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	4.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 time.h	980 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 timer-regs.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	3.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	941 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vm_fault.h	993 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vm_mmu.h	3.37 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: cacheflush.h

/*
 * Cache flush operations for the Hexagon architecture
 *
 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
 * 02110-1301, USA.
 */

#ifndef _ASM_CACHEFLUSH_H
#define _ASM_CACHEFLUSH_H

#include <linux/mm_types.h>

/* Cache flushing:
 *
 *  - flush_cache_all() flushes entire cache
 *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
 *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page
 *  - flush_cache_range(vma, start, end) flushes a range of pages
 *  - flush_icache_range(start, end) flush a range of instructions
 *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
 *  - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
 *
 *  Need to doublecheck which one is really needed for ptrace stuff to work.
 */
#define LINESIZE	32
#define LINEBITS	5

#define flush_cache_all()			do { } while (0)
#define flush_cache_mm(mm)			do { } while (0)
#define flush_cache_dup_mm(mm)			do { } while (0)
#define flush_cache_range(vma, start, end)	do { } while (0)
#define flush_cache_page(vma, vmaddr, pfn)	do { } while (0)
#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
#define flush_dcache_page(page)			do { } while (0)
#define flush_dcache_mmap_lock(mapping)		do { } while (0)
#define flush_dcache_mmap_unlock(mapping)	do { } while (0)
#define flush_icache_page(vma, pg)		do { } while (0)
#define flush_icache_user_range(vma, pg, adr, len)	do { } while (0)
#define flush_cache_vmap(start, end)		do { } while (0)
#define flush_cache_vunmap(start, end)		do { } while (0)

/*
 * Flush Dcache range through current map.
 */
extern void flush_dcache_range(unsigned long start, unsigned long end);

/*
 * Flush Icache range through current map.
 */
extern void flush_icache_range(unsigned long start, unsigned long end);

/*
 * Memory-management related flushes are there to ensure in non-physically
 * indexed cache schemes that stale lines belonging to a given ASID aren't
 * in the cache to confuse things.  The prototype Hexagon Virtual Machine
 * only uses a single ASID for all user-mode maps, which should
 * mean that they aren't necessary.  A brute-force, flush-everything
 * implementation, with the name xxxxx_hexagon() is present in
 * arch/hexagon/mm/cache.c, but let's not wire it up until we know
 * it is needed.
 */
extern void flush_cache_all_hexagon(void);

/*
 * This may or may not ever have to be non-null, depending on the
 * virtual machine MMU.  For a native kernel, it's definitiely  a no-op
 *
 * This is also the place where deferred cache coherency stuff seems
 * to happen, classically...  but instead we do it like ia64 and
 * clean the cache when the PTE is set.
 *
 */
static inline void update_mmu_cache(struct vm_area_struct *vma,
					unsigned long address, pte_t *ptep)
{
	/*  generic_ptrace_pokedata doesn't wind up here, does it?  */
}

void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
		       unsigned long vaddr, void *dst, void *src, int len);

#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
	memcpy(dst, src, len)

extern void hexagon_inv_dcache_range(unsigned long start, unsigned long end);
extern void hexagon_clean_dcache_range(unsigned long start, unsigned long end);

#endif