OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:15 AM	rwxr-xr-x
📄 Kbuild	681 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 arcregs.h	8.59 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 asm-offsets.h	311 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	15.14 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 barrier.h	1.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	9.81 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bug.h	938 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 cache.h	3.77 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cacheflush.h	3.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	2.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	5.4 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 current.h	695 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	1.99 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 disasm.h	3.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	734 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	459 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dwarf.h	892 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	2.15 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 entry-arcv2.h	4.85 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 entry-compact.h	9.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry.h	6.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	410 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	411 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	3.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugepage.h	2.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	6.42 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 irq.h	825 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags-arcv2.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags-compact.h	4.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	509 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	400 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	489 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	1.42 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mach_desc.h	2.06 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmu.h	2.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	5.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	989 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	661 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	2.99 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci.h	705 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	6.86 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgalloc.h	3.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	14.2 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 processor.h	4.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	3.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	407 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 segment.h	612 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	644 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	442 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	4.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	8.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	1.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscalls.h	653 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	3.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	508 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb-mmu1.h	3.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	1.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	18.45 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 unaligned.h	771 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unwind.h	3.51 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: perf_event.h

/*
 * Linux performance counter support for ARC
 *
 * Copyright (C) 2014-2015 Synopsys, Inc. (www.synopsys.com)
 * Copyright (C) 2011-2013 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef __ASM_PERF_EVENT_H
#define __ASM_PERF_EVENT_H

/* Max number of counters that PCT block may ever have */
#define ARC_PERF_MAX_COUNTERS	32

#define ARC_REG_CC_BUILD	0xF6
#define ARC_REG_CC_INDEX	0x240
#define ARC_REG_CC_NAME0	0x241
#define ARC_REG_CC_NAME1	0x242

#define ARC_REG_PCT_BUILD	0xF5
#define ARC_REG_PCT_COUNTL	0x250
#define ARC_REG_PCT_COUNTH	0x251
#define ARC_REG_PCT_SNAPL	0x252
#define ARC_REG_PCT_SNAPH	0x253
#define ARC_REG_PCT_CONFIG	0x254
#define ARC_REG_PCT_CONTROL	0x255
#define ARC_REG_PCT_INDEX	0x256
#define ARC_REG_PCT_INT_CNTL	0x25C
#define ARC_REG_PCT_INT_CNTH	0x25D
#define ARC_REG_PCT_INT_CTRL	0x25E
#define ARC_REG_PCT_INT_ACT	0x25F

#define ARC_REG_PCT_CONFIG_USER	(1 << 18)	/* count in user mode */
#define ARC_REG_PCT_CONFIG_KERN	(1 << 19)	/* count in kernel mode */

#define ARC_REG_PCT_CONTROL_CC	(1 << 16)	/* clear counts */
#define ARC_REG_PCT_CONTROL_SN	(1 << 17)	/* snapshot */

struct arc_reg_pct_build {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int m:8, c:8, r:5, i:1, s:2, v:8;
#else
	unsigned int v:8, s:2, i:1, r:5, c:8, m:8;
#endif
};

struct arc_reg_cc_build {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int c:16, r:8, v:8;
#else
	unsigned int v:8, r:8, c:16;
#endif
};

#define PERF_COUNT_ARC_DCLM	(PERF_COUNT_HW_MAX + 0)
#define PERF_COUNT_ARC_DCSM	(PERF_COUNT_HW_MAX + 1)
#define PERF_COUNT_ARC_ICM	(PERF_COUNT_HW_MAX + 2)
#define PERF_COUNT_ARC_BPOK	(PERF_COUNT_HW_MAX + 3)
#define PERF_COUNT_ARC_EDTLB	(PERF_COUNT_HW_MAX + 4)
#define PERF_COUNT_ARC_EITLB	(PERF_COUNT_HW_MAX + 5)
#define PERF_COUNT_ARC_LDC	(PERF_COUNT_HW_MAX + 6)
#define PERF_COUNT_ARC_STC	(PERF_COUNT_HW_MAX + 7)

#define PERF_COUNT_ARC_HW_MAX	(PERF_COUNT_HW_MAX + 8)

/*
 * Some ARC pct quirks:
 *
 * PERF_COUNT_HW_STALLED_CYCLES_BACKEND
 * PERF_COUNT_HW_STALLED_CYCLES_FRONTEND
 *	The ARC 700 can either measure stalls per pipeline stage, or all stalls
 *	combined; for now we assign all stalls to STALLED_CYCLES_BACKEND
 *	and all pipeline flushes (e.g. caused by mispredicts, etc.) to
 *	STALLED_CYCLES_FRONTEND.
 *
 *	We could start multiple performance counters and combine everything
 *	afterwards, but that makes it complicated.
 *
 *	Note that I$ cache misses aren't counted by either of the two!
 */

/*
 * ARC PCT has hardware conditions with fixed "names" but variable "indexes"
 * (based on a specific RTL build)
 * Below is the static map between perf generic/arc specific event_id and
 * h/w condition names.
 * At the time of probe, we loop thru each index and find it's name to
 * complete the mapping of perf event_id to h/w index as latter is needed
 * to program the counter really
 */
static const char * const arc_pmu_ev_hw_map[] = {
	/* count cycles */
	[PERF_COUNT_HW_CPU_CYCLES] = "crun",
	[PERF_COUNT_HW_REF_CPU_CYCLES] = "crun",
	[PERF_COUNT_HW_BUS_CYCLES] = "crun",

[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = "bflush",
	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = "bstall",

/* counts condition */
	[PERF_COUNT_HW_INSTRUCTIONS] = "iall",
	/* All jump instructions that are taken */
	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = "ijmptak",
	[PERF_COUNT_ARC_BPOK]         = "bpok",	  /* NP-NT, PT-T, PNT-NT */
#ifdef CONFIG_ISA_ARCV2
	[PERF_COUNT_HW_BRANCH_MISSES] = "bpmp",
#else
	[PERF_COUNT_HW_BRANCH_MISSES] = "bpfail", /* NP-T, PT-NT, PNT-T */
#endif
	[PERF_COUNT_ARC_LDC] = "imemrdc",	/* Instr: mem read cached */
	[PERF_COUNT_ARC_STC] = "imemwrc",	/* Instr: mem write cached */

[PERF_COUNT_ARC_DCLM] = "dclm",		/* D-cache Load Miss */
	[PERF_COUNT_ARC_DCSM] = "dcsm",		/* D-cache Store Miss */
	[PERF_COUNT_ARC_ICM] = "icm",		/* I-cache Miss */
	[PERF_COUNT_ARC_EDTLB] = "edtlb",	/* D-TLB Miss */
	[PERF_COUNT_ARC_EITLB] = "eitlb",	/* I-TLB Miss */

[PERF_COUNT_HW_CACHE_REFERENCES] = "imemrdc",	/* Instr: mem read cached */
	[PERF_COUNT_HW_CACHE_MISSES] = "dclm",		/* D-cache Load Miss */
};

#define C(_x)			PERF_COUNT_HW_CACHE_##_x
#define CACHE_OP_UNSUPPORTED	0xffff

static const unsigned arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
	[C(L1D)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= PERF_COUNT_ARC_LDC,
			[C(RESULT_MISS)]	= PERF_COUNT_ARC_DCLM,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= PERF_COUNT_ARC_STC,
			[C(RESULT_MISS)]	= PERF_COUNT_ARC_DCSM,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(L1I)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= PERF_COUNT_HW_INSTRUCTIONS,
			[C(RESULT_MISS)]	= PERF_COUNT_ARC_ICM,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(LL)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(DTLB)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= PERF_COUNT_ARC_LDC,
			[C(RESULT_MISS)]	= PERF_COUNT_ARC_EDTLB,
		},
			/* DTLB LD/ST Miss not segregated by h/w*/
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(ITLB)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= PERF_COUNT_ARC_EITLB,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(BPU)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
			[C(RESULT_MISS)]	= PERF_COUNT_HW_BRANCH_MISSES,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
	[C(NODE)] = {
		[C(OP_READ)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_WRITE)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
		[C(OP_PREFETCH)] = {
			[C(RESULT_ACCESS)]	= CACHE_OP_UNSUPPORTED,
			[C(RESULT_MISS)]	= CACHE_OP_UNSUPPORTED,
		},
	},
};

#endif /* __ASM_PERF_EVENT_H */