OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:15 AM	rwxr-xr-x
📄 8250_pci.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 a.out.h	354 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 acct.h	2.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 acpi.h	36.89 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 acpi_dma.h	3.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 acpi_iort.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 acpi_pmtmr.h	674 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 adb.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 adfs_fs.h	574 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 aer.h	1.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 agp_backend.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 agpgart.h	3.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ahci-remap.h	607 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ahci_platform.h	1.67 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 aio.h	673 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 alarmtimer.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 altera_jtaguart.h	379 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 altera_uart.h	397 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 amba	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 amd-iommu.h	6.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amifd.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 amifdreg.h	2.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 anon_inodes.h	494 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 apm-emulation.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apm_bios.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apple-gmux.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 apple_bl.h	498 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 arch_topology.h	840 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 arm-cci.h	2.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 arm-smccc.h	12.79 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 arm_sdei.h	2.33 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 asn1.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asn1_ber_bytecode.h	2.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asn1_decoder.h	675 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 assoc_array.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 assoc_array_priv.h	5.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 async.h	1.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 async_tx.h	6.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ata.h	33.61 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ata_platform.h	729 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atalk.h	4.36 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ath9k_platform.h	1.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atm.h	287 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atm_suni.h	253 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atm_tcp.h	511 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atmdev.h	10.21 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 atmel-mci.h	1.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atmel-ssc.h	9.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atmel_pdc.h	1.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atmel_tc.h	11.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	30.5 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 attribute_container.h	2.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 audit.h	17.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 auto_dev-ioctl.h	454 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 auto_fs.h	436 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 auxvec.h	304 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 average.h	2.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 avf	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 b1pcmcia.h	666 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 backing-dev-defs.h	8.53 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 backing-dev.h	13.8 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 backlight.h	5.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 badblocks.h	2.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 balloon_compaction.h	7.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcd.h	559 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bch.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcm47xx_nvram.h	1.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcm47xx_sprom.h	600 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcm47xx_wdt.h	555 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcm963xx_nvram.h	2.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcm963xx_tag.h	3.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 bcma	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 bfin_mac.h	559 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 binfmts.h	4.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bio.h	20.17 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bit_spinlock.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitfield.h	3.2 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bitmap.h	16.68 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bitops.h	6.69 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bitrev.h	2.53 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bits.h	883 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 blk-cgroup.h	22.2 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 blk-mq-pci.h	247 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 blk-mq-rdma.h	232 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 blk-mq-virtio.h	288 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 blk-mq.h	9.09 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 blk_types.h	10.52 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 blkdev.h	58.96 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 blkpg.h	436 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 blktrace_api.h	3.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 blockgroup_lock.h	810 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bma150.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bootmem.h	11.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bottom_half.h	803 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bpf-cgroup.h	4.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bpf.h	18.51 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bpf_trace.h	196 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bpf_types.h	1.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bpf_verifier.h	6.76 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 brcmphy.h	9.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bsearch.h	275 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bsg-lib.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bsg.h	773 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 btree-128.h	2.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 btree-type.h	3.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 btree.h	6.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 btrfs.h	145 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 buffer_head.h	14.38 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bug.h	1.92 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 build_bug.h	3.15 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bvec.h	4.39 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 byteorder	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 c2port.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheinfo.h	3.27 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 can	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 capability.h	7.6 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cb710.h	5.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cciss_ioctl.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ccp.h	18.26 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cdev.h	845 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cdrom.h	8.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 ceph	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 cfag12864b.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cgroup-defs.h	25.38 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cgroup.h	26.12 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cgroup_rdma.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cgroup_subsys.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 circ_buf.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cleancache.h	3.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 clk	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 clk-provider.h	34.29 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 clk.h	19.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clkdev.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clock_cooling.h	2.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clockchips.h	7.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocksource.h	8.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cm4000_cs.h	199 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cma.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmdline-parser.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cn_proc.h	1.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cnt32_to_63.h	3.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 coda.h	2.16 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 coda_psdev.h	2.98 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compaction.h	7.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	27.39 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compiler-clang.h	1.31 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compiler-gcc.h	12.6 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compiler-intel.h	1.3 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compiler.h	10.06 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compiler_types.h	7.5 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 completion.h	4.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 component.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 concap.h	3.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 configfs.h	9.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 connector.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 console.h	6.72 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 console_struct.h	6.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 consolemap.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 const.h	157 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 container.h	668 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 context_tracking.h	4.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 context_tracking_state.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cordic.h	1.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 coredump.h	783 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 coresight-pmu.h	1.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 coresight-stm.h	152 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 coresight.h	9.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 count_zeros.h	1.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cper.h	16.11 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu.h	6.86 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpu_cooling.h	3.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu_pm.h	2.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu_rmap.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpufeature.h	1.85 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpufreq.h	27.62 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpuhotplug.h	12.05 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpuidle.h	8.68 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpumask.h	25.38 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpuset.h	7.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 crash_core.h	2.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 crash_dump.h	2.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc-ccitt.h	369 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc-itu-t.h	613 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc-t10dif.h	415 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc16.h	622 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc32.h	2.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc32c.h	293 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc4.h	192 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc7.h	316 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crc8.h	3.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cred.h	12.29 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 crush	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 crypto.h	55.52 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cryptohash.h	319 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cs5535.h	6.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ctype.h	1.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cuda.h	501 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cyclades.h	10.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 davinci_emac.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dax.h	3.65 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dca.h	2.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcache.h	18.78 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dccp.h	10.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcookies.h	1.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug_locks.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debugfs.h	11.09 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 debugobjects.h	3.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 decompress	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 delay.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delayacct.h	5.17 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 delayed_call.h	709 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dell-led.h	128 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 devcoredump.h	2.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 devfreq-event.h	5.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 devfreq.h	12.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 devfreq_cooling.h	3.54 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 device-mapper.h	17.85 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 device.h	55.51 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 device_cgroup.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 devpts_fs.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 digsig.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dim.h	8.98 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dio.h	10.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dirent.h	216 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dlm.h	6.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dlm_plock.h	678 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dm-dirty-log.h	3.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dm-io.h	1.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dm-kcopyd.h	2.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dm-region-hash.h	3.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dm9000.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 dma	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 dma-buf.h	14.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-contiguous.h	4.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-debug.h	5.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-direction.h	338 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-fence-array.h	2.49 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dma-fence.h	17.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-iommu.h	3.62 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dma-mapping.h	24.61 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dma_remapping.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dmaengine.h	46.04 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dmapool.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dmar.h	7.94 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dmi.h	4.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dnotify.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dns_resolver.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dqblk_qtree.h	2.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dqblk_v1.h	327 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dqblk_v2.h	406 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 drbd.h	10.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 drbd_genl.h	21.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 drbd_genl_api.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 drbd_limits.h	7.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ds2782_battery.h	158 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 dsa	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 dtlk.h	3.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dw_apb_timer.h	1.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dynamic_debug.h	5.08 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dynamic_queue_limits.h	3.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 earlycpio.h	359 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ecryptfs.h	3.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 edac.h	20.26 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 edd.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 edma.h	807 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeprom_93cx6.h	2.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeprom_93xx46.h	879 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 efi-bgrt.h	644 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 efi.h	49.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 efs_vh.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eisa.h	2.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elevator.h	9.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf-fdpic.h	2.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf-randomize.h	583 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	1.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elfcore-compat.h	1.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elfcore.h	2.52 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 elfnote.h	3.54 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 enclosure.h	4.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 err.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 errno.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 errqueue.h	524 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 errseq.h	373 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 etherdevice.h	15.65 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ethtool.h	17.3 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 eventfd.h	2.36 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 eventpoll.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 evm.h	2.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 export.h	3.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exportfs.h	7.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ext2_fs.h	967 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	999 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 extcon	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 extcon-provider.h	4.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 extcon.h	10.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 f2fs_fs.h	17.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 f75375s.h	541 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 falloc.h	792 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fanotify.h	245 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fault-inject.h	1.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	28.74 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 fbcon.h	492 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 fcdevice.h	988 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fcntl.h	1.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fd.h	490 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fddidevice.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fdtable.h	3.28 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 fec.h	609 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 file.h	2.18 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 filter.h	27.5 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 fips.h	167 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 firewire.h	13.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 firmware	-	05/09/2024 07:14:14 AM	rwxr-xr-x
📄 firmware-map.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 firmware.h	2.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixp-arith.h	4.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	1.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flex_array.h	4.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 flex_proportions.h	2.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fmc-sdb.h	1.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fmc.h	9.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 font.h	1.6 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 fpga	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 frame.h	813 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 freezer.h	8.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 frontswap.h	2.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs.h	110.97 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 fs_enet_pd.h	3.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs_pin.h	619 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs_stack.h	811 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs_struct.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs_uart_pd.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fscache-cache.h	18.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 fscache.h	27.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fscrypt.h	8.93 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 fscrypt_notsupp.h	4.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fscrypt_supp.h	6.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsi.h	2.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 fsl	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 fsl-diu-fb.h	4.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_devices.h	4.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_hypervisor.h	2.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_ifc.h	25.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 fsldma.h	398 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsnotify.h	7.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsnotify_backend.h	16.66 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ftrace.h	29.91 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ftrace_irq.h	823 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 fwnode.h	4.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gameport.h	5.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gcd.h	193 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 genalloc.h	5.92 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 genetlink.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 genhd.h	22.77 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 genl_magic_func.h	12.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 genl_magic_struct.h	7.66 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 getcpu.h	641 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 gfp.h	23.37 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 glob.h	256 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 goldfish.h	605 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 gpio	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 gpio-pxa.h	571 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 gpio.h	5.19 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 gpio_keys.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	1.95 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hash.h	3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hashtable.h	6.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hdlc.h	3.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hdlcdrv.h	6.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hdmi.h	9.36 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hid-debug.h	2.07 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hid-roccat.h	688 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hid-sensor-hub.h	9.25 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hid-sensor-ids.h	7.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hid.h	35.93 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hiddev.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hidraw.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	5.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highuid.h	3.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hil.h	18.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hil_mlc.h	5.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hippidevice.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hmm.h	18.19 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 host1x.h	9.02 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hp_sdc.h	14.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hpet.h	2.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hrtimer.h	14.02 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 hsi	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 htcpld.h	617 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 huge_mm.h	10.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hugetlb.h	17 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hugetlb_cgroup.h	2.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb_inline.h	374 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	3.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_random.h	2.03 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hwmon-sysfs.h	1.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwmon-vid.h	1.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwmon.h	12.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hwspinlock.h	11.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hyperv.h	38.89 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hypervisor.h	400 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 i2c	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 i2c-algo-bit.h	2.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-algo-pca.h	2.89 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 i2c-algo-pcf.h	1.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-dev.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-gpio.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-mux-gpio.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-mux.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-ocores.h	757 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-omap.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-pca-platform.h	441 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-pnx.h	923 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-pxa.h	438 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-smbus.h	1.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c-xiic.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i2c.h	30.91 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 i7300_idle.h	1.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8042.h	2.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8253.h	809 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 icmp.h	863 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 icmpv6.h	2.5 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ide.h	46.27 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 idr.h	7.82 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ieee80211.h	83.19 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ieee802154.h	11.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_arp.h	1.86 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 if_bridge.h	2.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_eql.h	1.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_ether.h	1.47 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 if_fddi.h	3.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_frad.h	2.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_link.h	554 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_ltalk.h	188 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_macvlan.h	2.2 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 if_phonet.h	319 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_pppol2tp.h	727 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_pppox.h	3.05 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 if_tap.h	2.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_team.h	7.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_tun.h	1.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_tunnel.h	409 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 if_vlan.h	19.2 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 igmp.h	4.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ihex.h	1.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 iio	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 ima.h	2.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 imx-media.h	811 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 in.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 in6.h	1.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 inet.h	2.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 inet_diag.h	2.42 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 inetdevice.h	8.25 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 init.h	9.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 init_ohci1394_dma.h	196 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 init_task.h	7.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 initrd.h	685 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 inotify.h	696 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 input	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 input-polldev.h	2.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 input.h	18.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 integrity.h	1.05 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 intel-iommu.h	16.85 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 intel-pti.h	1.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel-svm.h	4.96 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 interrupt.h	21.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 interval_tree.h	831 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 interval_tree_generic.h	8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-64-nonatomic-hi-lo.h	1.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-64-nonatomic-lo-hi.h	1.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-mapping.h	4.36 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 io.h	5.86 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ioc3.h	3.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📁 irqchip	-	05/09/2024 07:14:16 AM	rwxr-xr-x
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📄 irqdesc.h	8.15 KB	06/16/2023 05:32:39 PM	rw-r--r--
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📁 lockd	-	05/09/2024 07:14:16 AM	rwxr-xr-x
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📄 memstick.h	9.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 mfd	-	05/09/2024 07:14:16 AM	rwxr-xr-x
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📄 micrel_phy.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 migrate.h	10.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 migrate_mode.h	758 bytes	01/28/2018 09:20:33 PM	rw-r--r--
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📄 miscdevice.h	2.81 KB	06/16/2023 05:32:39 PM	rw-r--r--
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📄 mm-arch-hooks.h	679 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mm.h	85.89 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mm_inline.h	3.44 KB	06/16/2023 05:32:39 PM	rw-r--r--
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📄 mman.h	3.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 mmc	-	05/09/2024 07:14:16 AM	rwxr-xr-x
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📄 mmiotrace.h	3.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	378 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_notifier.h	15.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	39.66 KB	06/16/2023 05:32:39 PM	rw-r--r--
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📄 msi.h	11.79 KB	06/16/2023 05:32:39 PM	rw-r--r--
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📄 mutex.h	6.91 KB	06/16/2023 05:32:39 PM	rw-r--r--
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📄 mv643xx.h	52.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📁 netfilter	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 netfilter.h	11.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 netfilter_arp	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📁 netfilter_bridge	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 netfilter_bridge.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 netfilter_ingress.h	1.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 netfilter_ipv4	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 netfilter_ipv4.h	424 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 netfilter_ipv6	-	05/09/2024 07:14:16 AM	rwxr-xr-x
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📄 nfs_fs_sb.h	8.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nfs_iostat.h	4.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nfs_page.h	6.26 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 nfs_xdr.h	38.79 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 nfsacl.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nl802154.h	4.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nls.h	3.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nmi.h	6.56 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 node.h	3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nodemask.h	17.08 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 nospec.h	2.21 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 notifier.h	7.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ns_common.h	235 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nsc_gpio.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nsproxy.h	2.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ntb.h	46.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ntb_transport.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nubus.h	4.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 numa.h	292 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvme-fc-driver.h	38.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvme-fc.h	8.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvme-rdma.h	2.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvme.h	26.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvmem-consumer.h	4.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvmem-provider.h	1.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nvram.h	495 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 of.h	40.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 of_address.h	4.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_device.h	3.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_dma.h	2.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_fdt.h	4.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_gpio.h	4.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_graph.h	3.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_iommu.h	1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_irq.h	3.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_mdio.h	2.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_net.h	708 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_pci.h	2.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_pdt.h	1.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_platform.h	4.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 of_reserved_mem.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 oid_registry.h	3.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 olpc-ec.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 omap-dma.h	10.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 omap-dmaengine.h	583 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 omap-gpmc.h	2.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 omap-iommu.h	520 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 omap-mailbox.h	777 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 omapfb.h	1.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 once.h	2.8 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 oom.h	3.15 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 openvswitch.h	844 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 oprofile.h	6.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 osq_lock.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 overflow.h	9.26 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 oxu210hp.h	197 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 padata.h	5.82 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 page-flags-layout.h	2.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page-flags.h	23.91 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 page-isolation.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_counter.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_ext.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_idle.h	2.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_owner.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_ref.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pageblock-flags.h	3.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pagemap.h	19.02 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pagevec.h	2.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 parman.h	2.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 parport.h	17.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 parport_pc.h	6.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 parser.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pata_arasan_cf_data.h	1.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 patchkey.h	757 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 path.h	572 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pch_dma.h	999 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-acpi.h	3.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-aspm.h	882 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 pci-ats.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-dma-compat.h	4.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-dma.h	454 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-ecam.h	2.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-ep-cfs.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-epc.h	5.38 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pci-epf.h	4.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	81.59 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pci_hotplug.h	6.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_ids.h	120.12 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pcieport_if.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pda_power.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pe.h	15.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu-defs.h	18.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 percpu-refcount.h	9.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu-rwsem.h	4.09 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 percpu.h	5.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu_counter.h	4.26 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 percpu_ida.h	2.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 perf	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 perf_event.h	38.78 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 perf_regs.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 personality.h	393 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pfn.h	666 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pfn_t.h	3.23 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 phonet.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 phy	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 phy.h	31.11 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 phy_fixed.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 phy_led_triggers.h	1.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 phylink.h	5.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pid.h	5.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pid_namespace.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pim.h	2.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 pinctrl	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 pipe_fs_i.h	6.46 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pkeys.h	916 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pktcdvd.h	5.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pl320-ipc.h	758 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 platform_data	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 platform_device.h	12.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 plist.h	8.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm-trace.h	940 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm.h	34.21 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pm2301_charger.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm_clock.h	2.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm_domain.h	9.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm_opp.h	10.08 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pm_qos.h	8.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm_runtime.h	8.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm_wakeirq.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm_wakeup.h	6.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmbus.h	1.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmu.h	2.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pnfs_osd_xdr.h	9.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pnp.h	14.89 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 poison.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 poll.h	3.24 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 posix-clock.h	4.55 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 posix-timers.h	3.55 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 posix_acl.h	3.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 posix_acl_xattr.h	1.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 power	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 power_supply.h	13.41 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 powercap.h	12.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppp-comp.h	3.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppp_channel.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppp_defs.h	454 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pps-gpio.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pps_kernel.h	3.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pr.h	566 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 prandom.h	2.81 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 preempt.h	9.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prefetch.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prime_numbers.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 printk.h	15.24 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 proc_fs.h	3.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 proc_ns.h	2.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	2.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 profile.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 projid.h	2.34 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 property.h	9.79 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 psci.h	1.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pstore.h	7.58 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pstore_ram.h	2.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pti.h	240 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 ptp_classify.h	2.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptp_clock_kernel.h	8.56 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ptr_ring.h	16.29 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ptrace.h	14.57 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 purgatory.h	589 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pvclock_gtod.h	548 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pwm.h	16.8 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pwm_backlight.h	740 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pxa168_eth.h	728 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pxa2xx_ssp.h	9.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 qcom_scm.h	4.12 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 qed	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 qnx6_fs.h	3.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 quicklist.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 quota.h	18.87 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 quotaops.h	10.17 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 radix-tree.h	21.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 raid	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 raid_class.h	2.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ramfs.h	762 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 random.h	3.98 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 range.h	651 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ras.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ratelimit.h	2.81 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 rational.h	639 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rbtree.h	5.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rbtree_augmented.h	8.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rbtree_latch.h	6.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rcu_node_tree.h	4.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rcu_segcblist.h	3.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rcu_sync.h	2.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rculist.h	23.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rculist_bl.h	4.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rculist_nulls.h	6.17 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 rcupdate.h	33.26 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 rcupdate_wait.h	1.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rcutiny.h	3.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rcutree.h	3.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rcuwait.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reboot-mode.h	600 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 reboot.h	2.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reciprocal_div.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 refcount.h	2.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 regmap.h	42.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 regset.h	15.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 regulator	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 relay.h	8.84 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 remoteproc	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 remoteproc.h	18.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reservation.h	8.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 reset	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 reset-controller.h	2.16 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 reset.h	13.69 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 resource.h	339 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 resource_ext.h	2.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 restart_block.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rfkill.h	9.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rhashtable.h	38.24 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ring_buffer.h	6.79 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 rio.h	19.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rio_drv.h	14.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rio_ids.h	1.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rio_regs.h	19.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rmap.h	9.08 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 rmi.h	12.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rndis.h	16.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rodata_test.h	559 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 root_dev.h	579 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📁 rpmsg	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 rpmsg.h	8.37 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 rslib.h	2.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 rtc	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 rtc.h	8.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rtmutex.h	3.47 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 rtnetlink.h	4.27 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 rtsx_common.h	1.44 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 rtsx_pci.h	40.14 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 rtsx_usb.h	15.95 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 rwlock.h	4.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rwlock_api_smp.h	7.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rwlock_types.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rwsem-spinlock.h	1.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rwsem.h	6 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 s3c_adc_battery.h	971 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sa11x0-dma.h	572 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sbitmap.h	13.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scatterlist.h	13.29 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 scc.h	2.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 sched	-	05/09/2024 07:14:16 AM	rwxr-xr-x
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📄 sched_clock.h	661 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 scif.h	58.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scpi_protocol.h	2.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 screen_info.h	191 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sctp.h	21.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scx200.h	1.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scx200_gpio.h	2.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sdb.h	4.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sdla.h	6.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	2.66 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 securebits.h	239 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 security.h	47.81 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 sed-opal.h	1.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 seg6_hmac.h	136 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 seg6_iptunnel.h	148 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 seg6_local.h	100 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 selection.h	1.41 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 selinux.h	910 bytes	01/28/2018 09:20:33 PM	rw-r--r--
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📄 semaphore.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seq_buf.h	3.15 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 seq_file.h	6.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seq_file_net.h	713 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 seqlock.h	16.48 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 seqno-fence.h	3.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serdev.h	9.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	630 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial_8250.h	6.01 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 serial_bcm63xx.h	4.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial_core.h	17.72 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 serial_max3100.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial_pnx8xxx.h	2.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial_s3c.h	9.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial_sci.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serio.h	4.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 set_memory.h	740 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfi.h	5.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfi_acpi.h	3.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfp.h	10.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sh_clk.h	5.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sh_dma.h	3.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sh_eth.h	417 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sh_intc.h	3.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sh_timer.h	172 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shdma-base.h	4.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 shm.h	1.71 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 shmem_fs.h	5.33 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 shrinker.h	2.82 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 signal.h	12.57 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 signal_types.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 signalfd.h	817 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 siphash.h	5.59 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 sirfsoc_dma.h	162 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sizes.h	1.26 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 skb_array.h	5.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 skbuff.h	120.16 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 slab.h	21.45 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 slab_def.h	2.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 slub_def.h	5.44 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 sm501-regs.h	11.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sm501.h	4.63 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smc911x.h	294 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smc91x.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	5.67 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 smpboot.h	2.17 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 smsc911x.h	2.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smscphy.h	1.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 soc	-	05/09/2024 07:14:15 AM	rwxr-xr-x
📄 sock_diag.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 socket.h	11.35 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 sonet.h	469 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sony-laptop.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sonypi.h	2.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sort.h	247 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sound.h	807 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 soundcard.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 spi	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 spinlock.h	11.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_api_smp.h	5.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_api_up.h	3.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types_up.h	726 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_up.h	2.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 splice.h	3.01 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 spmi.h	5.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sram.h	844 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 srcu.h	6.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 srcutiny.h	3.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 srcutree.h	5.15 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 ssb	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 ssbi.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackdepot.h	967 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stackprotector.h	324 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	1.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 start_kernel.h	334 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stat.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 statfs.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 static_key.h	30 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stddef.h	620 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ste_modem_shm.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stm.h	4.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stmmac.h	5.39 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 stmp3xxx_rtc_wdt.h	332 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stmp_device.h	619 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stop_machine.h	4.68 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 string.h	14.97 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 string_helpers.h	2.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stringhash.h	2.65 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 stringify.h	341 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sudmac.h	1.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sungem_phy.h	3.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 sunrpc	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 sunserialcore.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sunxi-rsb.h	2.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 superhyway.h	2.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 suspend.h	19.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 svga.h	3.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 swap.h	21.58 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 swap_cgroup.h	971 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 swap_slots.h	840 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 swapfile.h	556 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 swapops.h	9.27 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 swiotlb.h	3.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switchtec.h	8.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 sxgbe_platform.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sync_file.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 synclink.h	989 bytes	01/28/2018 09:20:33 PM	rw-r--r--
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📄 sys_soc.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscalls.h	39.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscore_ops.h	635 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysctl.h	7.55 KB	06/16/2023 05:32:39 PM	rw-r--r--
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📄 syslog.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysrq.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sysv_fs.h	9.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 t10-pi.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 task_io_accounting.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 task_io_accounting_ops.h	2.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 task_work.h	617 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 taskstats_kern.h	957 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tboot.h	3.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tc.h	3.45 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tca6416_keypad.h	847 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tcp.h	15.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tee_drv.h	8.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 textsearch.h	4.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 textsearch_fsm.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tfrc.h	1.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thermal.h	19.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thinkpad_acpi.h	320 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	4.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 threads.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thunderbolt.h	19.02 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ti_wilink_st.h	14.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tick.h	7.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tifm.h	4.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timb_dma.h	1.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timb_gpio.h	1.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 time.h	3.71 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 time32.h	5.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 time64.h	4.01 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 timecounter.h	4.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timekeeper_internal.h	5.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timekeeping.h	5.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timekeeping32.h	3.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 timer.h	6.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timerfd.h	508 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 timeriomem-rng.h	475 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 timerqueue.h	1.19 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 timex.h	6.61 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tnum.h	2.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	4.85 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 torture.h	3.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 toshiba.h	904 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tpm.h	3 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tpm_command.h	847 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 trace.h	964 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 trace_clock.h	667 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 trace_events.h	16.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 trace_seq.h	3.74 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tracefs.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tracehook.h	7.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tracepoint-defs.h	778 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tracepoint.h	16.26 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 transport_class.h	2.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ts-nbus.h	532 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tsacct_kern.h	1.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tty.h	28.03 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tty_driver.h	15.45 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tty_flip.h	1.62 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 tty_ldisc.h	7.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 typecheck.h	624 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 types.h	5.61 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 u64_stats_sync.h	5.43 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 uaccess.h	9.95 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ucb1400.h	4.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucs2_string.h	662 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 udp.h	3.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uidgid.h	4.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uio.h	7.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uio_driver.h	4.07 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 ulpi	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 umh.h	1.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 unaligned	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 uprobes.h	6.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 usb	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 usb.h	75.97 KB	06/16/2023 05:32:39 PM	rw-r--r--
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📄 usbdevice_fs.h	2.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user-return-notifier.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	22 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user_namespace.h	4.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 util_macros.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 utsname.h	1.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
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Editing: dmaengine.h

/*
 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called COPYING.
 */
#ifndef LINUX_DMAENGINE_H
#define LINUX_DMAENGINE_H

#include <linux/device.h>
#include <linux/err.h>
#include <linux/uio.h>
#include <linux/bug.h>
#include <linux/scatterlist.h>
#include <linux/bitmap.h>
#include <linux/types.h>
#include <asm/page.h>

/**
 * typedef dma_cookie_t - an opaque DMA cookie
 *
 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
 */
typedef s32 dma_cookie_t;
#define DMA_MIN_COOKIE	1

static inline int dma_submit_error(dma_cookie_t cookie)
{
	return cookie < 0 ? cookie : 0;
}

/**
 * enum dma_status - DMA transaction status
 * @DMA_COMPLETE: transaction completed
 * @DMA_IN_PROGRESS: transaction not yet processed
 * @DMA_PAUSED: transaction is paused
 * @DMA_ERROR: transaction failed
 */
enum dma_status {
	DMA_COMPLETE,
	DMA_IN_PROGRESS,
	DMA_PAUSED,
	DMA_ERROR,
};

/**
 * enum dma_transaction_type - DMA transaction types/indexes
 *
 * Note: The DMA_ASYNC_TX capability is not to be set by drivers.  It is
 * automatically set as dma devices are registered.
 */
enum dma_transaction_type {
	DMA_MEMCPY,
	DMA_XOR,
	DMA_PQ,
	DMA_XOR_VAL,
	DMA_PQ_VAL,
	DMA_MEMSET,
	DMA_MEMSET_SG,
	DMA_INTERRUPT,
	DMA_PRIVATE,
	DMA_ASYNC_TX,
	DMA_SLAVE,
	DMA_CYCLIC,
	DMA_INTERLEAVE,
/* last transaction type for creation of the capabilities mask */
	DMA_TX_TYPE_END,
};

/**
 * enum dma_transfer_direction - dma transfer mode and direction indicator
 * @DMA_MEM_TO_MEM: Async/Memcpy mode
 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
 */
enum dma_transfer_direction {
	DMA_MEM_TO_MEM,
	DMA_MEM_TO_DEV,
	DMA_DEV_TO_MEM,
	DMA_DEV_TO_DEV,
	DMA_TRANS_NONE,
};

/**
 * Interleaved Transfer Request
 * ----------------------------
 * A chunk is collection of contiguous bytes to be transfered.
 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
 * ICGs may or maynot change between chunks.
 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
 *  that when repeated an integral number of times, specifies the transfer.
 * A transfer template is specification of a Frame, the number of times
 *  it is to be repeated and other per-transfer attributes.
 *
 * Practically, a client driver would have ready a template for each
 *  type of transfer it is going to need during its lifetime and
 *  set only 'src_start' and 'dst_start' before submitting the requests.
 *
 *
 *  |      Frame-1        |       Frame-2       | ~ |       Frame-'numf'  |
 *  |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
 *
 *    ==  Chunk size
 *    ... ICG
 */

/**
 * struct data_chunk - Element of scatter-gather list that makes a frame.
 * @size: Number of bytes to read from source.
 *	  size_dst := fn(op, size_src), so doesn't mean much for destination.
 * @icg: Number of bytes to jump after last src/dst address of this
 *	 chunk and before first src/dst address for next chunk.
 *	 Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
 *	 Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
 * @dst_icg: Number of bytes to jump after last dst address of this
 *	 chunk and before the first dst address for next chunk.
 *	 Ignored if dst_inc is true and dst_sgl is false.
 * @src_icg: Number of bytes to jump after last src address of this
 *	 chunk and before the first src address for next chunk.
 *	 Ignored if src_inc is true and src_sgl is false.
 */
struct data_chunk {
	size_t size;
	size_t icg;
	size_t dst_icg;
	size_t src_icg;
};

/**
 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
 *	 and attributes.
 * @src_start: Bus address of source for the first chunk.
 * @dst_start: Bus address of destination for the first chunk.
 * @dir: Specifies the type of Source and Destination.
 * @src_inc: If the source address increments after reading from it.
 * @dst_inc: If the destination address increments after writing to it.
 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
 *		Otherwise, source is read contiguously (icg ignored).
 *		Ignored if src_inc is false.
 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
 *		Otherwise, destination is filled contiguously (icg ignored).
 *		Ignored if dst_inc is false.
 * @numf: Number of frames in this template.
 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
 * @sgl: Array of {chunk,icg} pairs that make up a frame.
 */
struct dma_interleaved_template {
	dma_addr_t src_start;
	dma_addr_t dst_start;
	enum dma_transfer_direction dir;
	bool src_inc;
	bool dst_inc;
	bool src_sgl;
	bool dst_sgl;
	size_t numf;
	size_t frame_size;
	struct data_chunk sgl[0];
};

/**
 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
 *  control completion, and communicate status.
 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
 *  this transaction
 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
 *  acknowledges receipt, i.e. has has a chance to establish any dependency
 *  chains
 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
 *  sources that were the result of a previous operation, in the case of a PQ
 *  operation it continues the calculation with new sources
 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
 *  on the result of this operation
 * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
 *  cleared or freed
 * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
 *  data and the descriptor should be in different format from normal
 *  data descriptors.
 */
enum dma_ctrl_flags {
	DMA_PREP_INTERRUPT = (1 << 0),
	DMA_CTRL_ACK = (1 << 1),
	DMA_PREP_PQ_DISABLE_P = (1 << 2),
	DMA_PREP_PQ_DISABLE_Q = (1 << 3),
	DMA_PREP_CONTINUE = (1 << 4),
	DMA_PREP_FENCE = (1 << 5),
	DMA_CTRL_REUSE = (1 << 6),
	DMA_PREP_CMD = (1 << 7),
};

/**
 * enum sum_check_bits - bit position of pq_check_flags
 */
enum sum_check_bits {
	SUM_CHECK_P = 0,
	SUM_CHECK_Q = 1,
};

/**
 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
 */
enum sum_check_flags {
	SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
	SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
};

/**
 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
 * See linux/cpumask.h
 */
typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;

/**
 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
 * @memcpy_count: transaction counter
 * @bytes_transferred: byte counter
 */

struct dma_chan_percpu {
	/* stats */
	unsigned long memcpy_count;
	unsigned long bytes_transferred;
};

/**
 * struct dma_router - DMA router structure
 * @dev: pointer to the DMA router device
 * @route_free: function to be called when the route can be disconnected
 */
struct dma_router {
	struct device *dev;
	void (*route_free)(struct device *dev, void *route_data);
};

/**
 * struct dma_chan - devices supply DMA channels, clients use them
 * @device: ptr to the dma device who supplies this channel, always !%NULL
 * @cookie: last cookie value returned to client
 * @completed_cookie: last completed cookie for this channel
 * @chan_id: channel ID for sysfs
 * @dev: class device for sysfs
 * @device_node: used to add this to the device chan list
 * @local: per-cpu pointer to a struct dma_chan_percpu
 * @client_count: how many clients are using this channel
 * @table_count: number of appearances in the mem-to-mem allocation table
 * @router: pointer to the DMA router structure
 * @route_data: channel specific data for the router
 * @private: private data for certain client-channel associations
 */
struct dma_chan {
	struct dma_device *device;
	dma_cookie_t cookie;
	dma_cookie_t completed_cookie;

/* sysfs */
	int chan_id;
	struct dma_chan_dev *dev;

struct list_head device_node;
	struct dma_chan_percpu __percpu *local;
	int client_count;
	int table_count;

/* DMA router */
	struct dma_router *router;
	void *route_data;

void *private;
};

/**
 * struct dma_chan_dev - relate sysfs device node to backing channel device
 * @chan: driver channel device
 * @device: sysfs device
 * @dev_id: parent dma_device dev_id
 * @idr_ref: reference count to gate release of dma_device dev_id
 */
struct dma_chan_dev {
	struct dma_chan *chan;
	struct device device;
	int dev_id;
	atomic_t *idr_ref;
};

/**
 * enum dma_slave_buswidth - defines bus width of the DMA slave
 * device, source or target buses
 */
enum dma_slave_buswidth {
	DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
	DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
	DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
	DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
	DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
	DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
	DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
	DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
	DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
};

/**
 * struct dma_slave_config - dma slave channel runtime config
 * @direction: whether the data shall go in or out on this slave
 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
 * legal values. DEPRECATED, drivers should use the direction argument
 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
 * the dir field in the dma_interleaved_template structure.
 * @src_addr: this is the physical address where DMA slave data
 * should be read (RX), if the source is memory this argument is
 * ignored.
 * @dst_addr: this is the physical address where DMA slave data
 * should be written (TX), if the source is memory this argument
 * is ignored.
 * @src_addr_width: this is the width in bytes of the source (RX)
 * register where DMA data shall be read. If the source
 * is memory this may be ignored depending on architecture.
 * Legal values: 1, 2, 3, 4, 8, 16, 32, 64.
 * @dst_addr_width: same as src_addr_width but for destination
 * target (TX) mutatis mutandis.
 * @src_maxburst: the maximum number of words (note: words, as in
 * units of the src_addr_width member, not bytes) that can be sent
 * in one burst to the device. Typically something like half the
 * FIFO depth on I/O peripherals so you don't overflow it. This
 * may or may not be applicable on memory sources.
 * @dst_maxburst: same as src_maxburst but for destination target
 * mutatis mutandis.
 * @src_port_window_size: The length of the register area in words the data need
 * to be accessed on the device side. It is only used for devices which is using
 * an area instead of a single register to receive the data. Typically the DMA
 * loops in this area in order to transfer the data.
 * @dst_port_window_size: same as src_port_window_size but for the destination
 * port.
 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
 * with 'true' if peripheral should be flow controller. Direction will be
 * selected at Runtime.
 * @slave_id: Slave requester id. Only valid for slave channels. The dma
 * slave peripheral will have unique id as dma requester which need to be
 * pass as slave config.
 *
 * This struct is passed in as configuration data to a DMA engine
 * in order to set up a certain channel for DMA transport at runtime.
 * The DMA device/engine has to provide support for an additional
 * callback in the dma_device structure, device_config and this struct
 * will then be passed in as an argument to the function.
 *
 * The rationale for adding configuration information to this struct is as
 * follows: if it is likely that more than one DMA slave controllers in
 * the world will support the configuration option, then make it generic.
 * If not: if it is fixed so that it be sent in static from the platform
 * data, then prefer to do that.
 */
struct dma_slave_config {
	enum dma_transfer_direction direction;
	phys_addr_t src_addr;
	phys_addr_t dst_addr;
	enum dma_slave_buswidth src_addr_width;
	enum dma_slave_buswidth dst_addr_width;
	u32 src_maxburst;
	u32 dst_maxburst;
	u32 src_port_window_size;
	u32 dst_port_window_size;
	bool device_fc;
	unsigned int slave_id;
};

/**
 * enum dma_residue_granularity - Granularity of the reported transfer residue
 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
 *  DMA channel is only able to tell whether a descriptor has been completed or
 *  not, which means residue reporting is not supported by this channel. The
 *  residue field of the dma_tx_state field will always be 0.
 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
 *  completed segment of the transfer (For cyclic transfers this is after each
 *  period). This is typically implemented by having the hardware generate an
 *  interrupt after each transferred segment and then the drivers updates the
 *  outstanding residue by the size of the segment. Another possibility is if
 *  the hardware supports scatter-gather and the segment descriptor has a field
 *  which gets set after the segment has been completed. The driver then counts
 *  the number of segments without the flag set to compute the residue.
 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
 *  burst. This is typically only supported if the hardware has a progress
 *  register of some sort (E.g. a register with the current read/write address
 *  or a register with the amount of bursts/beats/bytes that have been
 *  transferred or still need to be transferred).
 */
enum dma_residue_granularity {
	DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
	DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
	DMA_RESIDUE_GRANULARITY_BURST = 2,
};

/**
 * struct dma_slave_caps - expose capabilities of a slave channel only
 * @src_addr_widths: bit mask of src addr widths the channel supports.
 *	Width is specified in bytes, e.g. for a channel supporting
 *	a width of 4 the mask should have BIT(4) set.
 * @dst_addr_widths: bit mask of dst addr widths the channel supports
 * @directions: bit mask of slave directions the channel supports.
 *	Since the enum dma_transfer_direction is not defined as bit flag for
 *	each type, the dma controller should set BIT(<TYPE>) and same
 *	should be checked by controller as well
 * @max_burst: max burst capability per-transfer
 * @cmd_pause: true, if pause and thereby resume is supported
 * @cmd_terminate: true, if terminate cmd is supported
 * @residue_granularity: granularity of the reported transfer residue
 * @descriptor_reuse: if a descriptor can be reused by client and
 * resubmitted multiple times
 */
struct dma_slave_caps {
	u32 src_addr_widths;
	u32 dst_addr_widths;
	u32 directions;
	u32 max_burst;
	bool cmd_pause;
	bool cmd_terminate;
	enum dma_residue_granularity residue_granularity;
	bool descriptor_reuse;
};

static inline const char *dma_chan_name(struct dma_chan *chan)
{
	return dev_name(&chan->dev->device);
}

void dma_chan_cleanup(struct kref *kref);

/**
 * typedef dma_filter_fn - callback filter for dma_request_channel
 * @chan: channel to be reviewed
 * @filter_param: opaque parameter passed through dma_request_channel
 *
 * When this optional parameter is specified in a call to dma_request_channel a
 * suitable channel is passed to this routine for further dispositioning before
 * being returned.  Where 'suitable' indicates a non-busy channel that
 * satisfies the given capability mask.  It returns 'true' to indicate that the
 * channel is suitable.
 */
typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);

typedef void (*dma_async_tx_callback)(void *dma_async_param);

enum dmaengine_tx_result {
	DMA_TRANS_NOERROR = 0,		/* SUCCESS */
	DMA_TRANS_READ_FAILED,		/* Source DMA read failed */
	DMA_TRANS_WRITE_FAILED,		/* Destination DMA write failed */
	DMA_TRANS_ABORTED,		/* Op never submitted / aborted */
};

struct dmaengine_result {
	enum dmaengine_tx_result result;
	u32 residue;
};

typedef void (*dma_async_tx_callback_result)(void *dma_async_param,
				const struct dmaengine_result *result);

struct dmaengine_unmap_data {
	u8 map_cnt;
	u8 to_cnt;
	u8 from_cnt;
	u8 bidi_cnt;
	struct device *dev;
	struct kref kref;
	size_t len;
	dma_addr_t addr[0];
};

/**
 * struct dma_async_tx_descriptor - async transaction descriptor
 * ---dma generic offload fields---
 * @cookie: tracking cookie for this transaction, set to -EBUSY if
 *	this tx is sitting on a dependency list
 * @flags: flags to augment operation preparation, control completion, and
 * 	communicate status
 * @phys: physical address of the descriptor
 * @chan: target channel for this operation
 * @tx_submit: accept the descriptor, assign ordered cookie and mark the
 * descriptor pending. To be pushed on .issue_pending() call
 * @callback: routine to call after this operation is complete
 * @callback_param: general parameter to pass to the callback routine
 * ---async_tx api specific fields---
 * @next: at completion submit this descriptor
 * @parent: pointer to the next level up in the dependency chain
 * @lock: protect the parent and next pointers
 */
struct dma_async_tx_descriptor {
	dma_cookie_t cookie;
	enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
	dma_addr_t phys;
	struct dma_chan *chan;
	dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
	int (*desc_free)(struct dma_async_tx_descriptor *tx);
	dma_async_tx_callback callback;
	dma_async_tx_callback_result callback_result;
	void *callback_param;
	struct dmaengine_unmap_data *unmap;
#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
	struct dma_async_tx_descriptor *next;
	struct dma_async_tx_descriptor *parent;
	spinlock_t lock;
#endif
};

#ifdef CONFIG_DMA_ENGINE
static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
				 struct dmaengine_unmap_data *unmap)
{
	kref_get(&unmap->kref);
	tx->unmap = unmap;
}

struct dmaengine_unmap_data *
dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
#else
static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
				 struct dmaengine_unmap_data *unmap)
{
}
static inline struct dmaengine_unmap_data *
dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
{
	return NULL;
}
static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
{
}
#endif

static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
{
	if (tx->unmap) {
		dmaengine_unmap_put(tx->unmap);
		tx->unmap = NULL;
	}
}

#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
static inline void txd_lock(struct dma_async_tx_descriptor *txd)
{
}
static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
{
}
static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
{
	BUG();
}
static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
{
}
static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
{
}
static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
{
	return NULL;
}
static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
{
	return NULL;
}

#else
static inline void txd_lock(struct dma_async_tx_descriptor *txd)
{
	spin_lock_bh(&txd->lock);
}
static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
{
	spin_unlock_bh(&txd->lock);
}
static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
{
	txd->next = next;
	next->parent = txd;
}
static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
{
	txd->parent = NULL;
}
static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
{
	txd->next = NULL;
}
static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
{
	return txd->parent;
}
static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
{
	return txd->next;
}
#endif

/**
 * struct dma_tx_state - filled in to report the status of
 * a transfer.
 * @last: last completed DMA cookie
 * @used: last issued DMA cookie (i.e. the one in progress)
 * @residue: the remaining number of bytes left to transmit
 *	on the selected transfer for states DMA_IN_PROGRESS and
 *	DMA_PAUSED if this is implemented in the driver, else 0
 */
struct dma_tx_state {
	dma_cookie_t last;
	dma_cookie_t used;
	u32 residue;
};

/**
 * enum dmaengine_alignment - defines alignment of the DMA async tx
 * buffers
 */
enum dmaengine_alignment {
	DMAENGINE_ALIGN_1_BYTE = 0,
	DMAENGINE_ALIGN_2_BYTES = 1,
	DMAENGINE_ALIGN_4_BYTES = 2,
	DMAENGINE_ALIGN_8_BYTES = 3,
	DMAENGINE_ALIGN_16_BYTES = 4,
	DMAENGINE_ALIGN_32_BYTES = 5,
	DMAENGINE_ALIGN_64_BYTES = 6,
};

/**
 * struct dma_slave_map - associates slave device and it's slave channel with
 * parameter to be used by a filter function
 * @devname: name of the device
 * @slave: slave channel name
 * @param: opaque parameter to pass to struct dma_filter.fn
 */
struct dma_slave_map {
	const char *devname;
	const char *slave;
	void *param;
};

/**
 * struct dma_filter - information for slave device/channel to filter_fn/param
 * mapping
 * @fn: filter function callback
 * @mapcnt: number of slave device/channel in the map
 * @map: array of channel to filter mapping data
 */
struct dma_filter {
	dma_filter_fn fn;
	int mapcnt;
	const struct dma_slave_map *map;
};

/**
 * struct dma_device - info on the entity supplying DMA services
 * @chancnt: how many DMA channels are supported
 * @privatecnt: how many DMA channels are requested by dma_request_channel
 * @channels: the list of struct dma_chan
 * @global_node: list_head for global dma_device_list
 * @filter: information for device/slave to filter function/param mapping
 * @cap_mask: one or more dma_capability flags
 * @max_xor: maximum number of xor sources, 0 if no capability
 * @max_pq: maximum number of PQ sources and PQ-continue capability
 * @copy_align: alignment shift for memcpy operations
 * @xor_align: alignment shift for xor operations
 * @pq_align: alignment shift for pq operations
 * @fill_align: alignment shift for memset operations
 * @dev_id: unique device ID
 * @dev: struct device reference for dma mapping api
 * @owner: owner module (automatically set based on the provided dev)
 * @src_addr_widths: bit mask of src addr widths the device supports
 *	Width is specified in bytes, e.g. for a device supporting
 *	a width of 4 the mask should have BIT(4) set.
 * @dst_addr_widths: bit mask of dst addr widths the device supports
 * @directions: bit mask of slave directions the device supports.
 *	Since the enum dma_transfer_direction is not defined as bit flag for
 *	each type, the dma controller should set BIT(<TYPE>) and same
 *	should be checked by controller as well
 * @max_burst: max burst capability per-transfer
 * @residue_granularity: granularity of the transfer residue reported
 *	by tx_status
 * @device_alloc_chan_resources: allocate resources and return the
 *	number of allocated descriptors
 * @device_free_chan_resources: release DMA channel's resources
 * @device_prep_dma_memcpy: prepares a memcpy operation
 * @device_prep_dma_xor: prepares a xor operation
 * @device_prep_dma_xor_val: prepares a xor validation operation
 * @device_prep_dma_pq: prepares a pq operation
 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
 * @device_prep_dma_memset: prepares a memset operation
 * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
 * @device_prep_slave_sg: prepares a slave dma operation
 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
 *	The function takes a buffer of size buf_len. The callback function will
 *	be called after period_len bytes have been transferred.
 * @device_prep_interleaved_dma: Transfer expression in a generic way.
 * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
 * @device_config: Pushes a new configuration to a channel, return 0 or an error
 *	code
 * @device_pause: Pauses any transfer happening on a channel. Returns
 *	0 or an error code
 * @device_resume: Resumes any transfer on a channel previously
 *	paused. Returns 0 or an error code
 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
 *	or an error code
 * @device_synchronize: Synchronizes the termination of a transfers to the
 *  current context.
 * @device_tx_status: poll for transaction completion, the optional
 *	txstate parameter can be supplied with a pointer to get a
 *	struct with auxiliary transfer status information, otherwise the call
 *	will just return a simple status code
 * @device_issue_pending: push pending transactions to hardware
 * @descriptor_reuse: a submitted transfer can be resubmitted after completion
 */
struct dma_device {

unsigned int chancnt;
	unsigned int privatecnt;
	struct list_head channels;
	struct list_head global_node;
	struct dma_filter filter;
	dma_cap_mask_t  cap_mask;
	unsigned short max_xor;
	unsigned short max_pq;
	enum dmaengine_alignment copy_align;
	enum dmaengine_alignment xor_align;
	enum dmaengine_alignment pq_align;
	enum dmaengine_alignment fill_align;
	#define DMA_HAS_PQ_CONTINUE (1 << 15)

int dev_id;
	struct device *dev;
	struct module *owner;

u32 src_addr_widths;
	u32 dst_addr_widths;
	u32 directions;
	u32 max_burst;
	bool descriptor_reuse;
	enum dma_residue_granularity residue_granularity;

int (*device_alloc_chan_resources)(struct dma_chan *chan);
	void (*device_free_chan_resources)(struct dma_chan *chan);

struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
		struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
		size_t len, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
		struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
		unsigned int src_cnt, size_t len, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
		struct dma_chan *chan, dma_addr_t *src,	unsigned int src_cnt,
		size_t len, enum sum_check_flags *result, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
		struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
		unsigned int src_cnt, const unsigned char *scf,
		size_t len, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
		struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
		unsigned int src_cnt, const unsigned char *scf, size_t len,
		enum sum_check_flags *pqres, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
		struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
		unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
		struct dma_chan *chan, struct scatterlist *sg,
		unsigned int nents, int value, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
		struct dma_chan *chan, unsigned long flags);

struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
		struct dma_chan *chan, struct scatterlist *sgl,
		unsigned int sg_len, enum dma_transfer_direction direction,
		unsigned long flags, void *context);
	struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
		size_t period_len, enum dma_transfer_direction direction,
		unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
		struct dma_chan *chan, struct dma_interleaved_template *xt,
		unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
		struct dma_chan *chan, dma_addr_t dst, u64 data,
		unsigned long flags);

int (*device_config)(struct dma_chan *chan,
			     struct dma_slave_config *config);
	int (*device_pause)(struct dma_chan *chan);
	int (*device_resume)(struct dma_chan *chan);
	int (*device_terminate_all)(struct dma_chan *chan);
	void (*device_synchronize)(struct dma_chan *chan);

enum dma_status (*device_tx_status)(struct dma_chan *chan,
					    dma_cookie_t cookie,
					    struct dma_tx_state *txstate);
	void (*device_issue_pending)(struct dma_chan *chan);
};

static inline int dmaengine_slave_config(struct dma_chan *chan,
					  struct dma_slave_config *config)
{
	if (chan->device->device_config)
		return chan->device->device_config(chan, config);

return -ENOSYS;
}

static inline bool is_slave_direction(enum dma_transfer_direction direction)
{
	return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
}

static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
	struct dma_chan *chan, dma_addr_t buf, size_t len,
	enum dma_transfer_direction dir, unsigned long flags)
{
	struct scatterlist sg;
	sg_init_table(&sg, 1);
	sg_dma_address(&sg) = buf;
	sg_dma_len(&sg) = len;

if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
		return NULL;

return chan->device->device_prep_slave_sg(chan, &sg, 1,
						  dir, flags, NULL);
}

static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
	struct dma_chan *chan, struct scatterlist *sgl,	unsigned int sg_len,
	enum dma_transfer_direction dir, unsigned long flags)
{
	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
		return NULL;

return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
						  dir, flags, NULL);
}

#ifdef CONFIG_RAPIDIO_DMA_ENGINE
struct rio_dma_ext;
static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
	struct dma_chan *chan, struct scatterlist *sgl,	unsigned int sg_len,
	enum dma_transfer_direction dir, unsigned long flags,
	struct rio_dma_ext *rio_ext)
{
	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
		return NULL;

return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
						  dir, flags, rio_ext);
}
#endif

static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
		size_t period_len, enum dma_transfer_direction dir,
		unsigned long flags)
{
	if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
		return NULL;

return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
						period_len, dir, flags);
}

static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
		struct dma_chan *chan, struct dma_interleaved_template *xt,
		unsigned long flags)
{
	if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
		return NULL;

return chan->device->device_prep_interleaved_dma(chan, xt, flags);
}

static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
		struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
		unsigned long flags)
{
	if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
		return NULL;

return chan->device->device_prep_dma_memset(chan, dest, value,
						    len, flags);
}

static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy(
		struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
		size_t len, unsigned long flags)
{
	if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)
		return NULL;

return chan->device->device_prep_dma_memcpy(chan, dest, src,
						    len, flags);
}

/**
 * dmaengine_terminate_all() - Terminate all active DMA transfers
 * @chan: The channel for which to terminate the transfers
 *
 * This function is DEPRECATED use either dmaengine_terminate_sync() or
 * dmaengine_terminate_async() instead.
 */
static inline int dmaengine_terminate_all(struct dma_chan *chan)
{
	if (chan->device->device_terminate_all)
		return chan->device->device_terminate_all(chan);

return -ENOSYS;
}

/**
 * dmaengine_terminate_async() - Terminate all active DMA transfers
 * @chan: The channel for which to terminate the transfers
 *
 * Calling this function will terminate all active and pending descriptors
 * that have previously been submitted to the channel. It is not guaranteed
 * though that the transfer for the active descriptor has stopped when the
 * function returns. Furthermore it is possible the complete callback of a
 * submitted transfer is still running when this function returns.
 *
 * dmaengine_synchronize() needs to be called before it is safe to free
 * any memory that is accessed by previously submitted descriptors or before
 * freeing any resources accessed from within the completion callback of any
 * perviously submitted descriptors.
 *
 * This function can be called from atomic context as well as from within a
 * complete callback of a descriptor submitted on the same channel.
 *
 * If none of the two conditions above apply consider using
 * dmaengine_terminate_sync() instead.
 */
static inline int dmaengine_terminate_async(struct dma_chan *chan)
{
	if (chan->device->device_terminate_all)
		return chan->device->device_terminate_all(chan);

return -EINVAL;
}

/**
 * dmaengine_synchronize() - Synchronize DMA channel termination
 * @chan: The channel to synchronize
 *
 * Synchronizes to the DMA channel termination to the current context. When this
 * function returns it is guaranteed that all transfers for previously issued
 * descriptors have stopped and and it is safe to free the memory assoicated
 * with them. Furthermore it is guaranteed that all complete callback functions
 * for a previously submitted descriptor have finished running and it is safe to
 * free resources accessed from within the complete callbacks.
 *
 * The behavior of this function is undefined if dma_async_issue_pending() has
 * been called between dmaengine_terminate_async() and this function.
 *
 * This function must only be called from non-atomic context and must not be
 * called from within a complete callback of a descriptor submitted on the same
 * channel.
 */
static inline void dmaengine_synchronize(struct dma_chan *chan)
{
	might_sleep();

if (chan->device->device_synchronize)
		chan->device->device_synchronize(chan);
}

/**
 * dmaengine_terminate_sync() - Terminate all active DMA transfers
 * @chan: The channel for which to terminate the transfers
 *
 * Calling this function will terminate all active and pending transfers
 * that have previously been submitted to the channel. It is similar to
 * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
 * stopped and that all complete callbacks have finished running when the
 * function returns.
 *
 * This function must only be called from non-atomic context and must not be
 * called from within a complete callback of a descriptor submitted on the same
 * channel.
 */
static inline int dmaengine_terminate_sync(struct dma_chan *chan)
{
	int ret;

ret = dmaengine_terminate_async(chan);
	if (ret)
		return ret;

dmaengine_synchronize(chan);

return 0;
}

static inline int dmaengine_pause(struct dma_chan *chan)
{
	if (chan->device->device_pause)
		return chan->device->device_pause(chan);

return -ENOSYS;
}

static inline int dmaengine_resume(struct dma_chan *chan)
{
	if (chan->device->device_resume)
		return chan->device->device_resume(chan);

return -ENOSYS;
}

static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
	dma_cookie_t cookie, struct dma_tx_state *state)
{
	return chan->device->device_tx_status(chan, cookie, state);
}

static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
{
	return desc->tx_submit(desc);
}

static inline bool dmaengine_check_align(enum dmaengine_alignment align,
					 size_t off1, size_t off2, size_t len)
{
	size_t mask;

if (!align)
		return true;
	mask = (1 << align) - 1;
	if (mask & (off1 | off2 | len))
		return false;
	return true;
}

static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
				       size_t off2, size_t len)
{
	return dmaengine_check_align(dev->copy_align, off1, off2, len);
}

static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
				      size_t off2, size_t len)
{
	return dmaengine_check_align(dev->xor_align, off1, off2, len);
}

static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
				     size_t off2, size_t len)
{
	return dmaengine_check_align(dev->pq_align, off1, off2, len);
}

static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
				       size_t off2, size_t len)
{
	return dmaengine_check_align(dev->fill_align, off1, off2, len);
}

static inline void
dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
{
	dma->max_pq = maxpq;
	if (has_pq_continue)
		dma->max_pq |= DMA_HAS_PQ_CONTINUE;
}

static inline bool dmaf_continue(enum dma_ctrl_flags flags)
{
	return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
}

static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
{
	enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;

return (flags & mask) == mask;
}

static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
{
	return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
}

static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
{
	return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
}

/* dma_maxpq - reduce maxpq in the face of continued operations
 * @dma - dma device with PQ capability
 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
 *
 * When an engine does not support native continuation we need 3 extra
 * source slots to reuse P and Q with the following coefficients:
 * 1/ {00} * P : remove P from Q', but use it as a source for P'
 * 2/ {01} * Q : use Q to continue Q' calculation
 * 3/ {00} * Q : subtract Q from P' to cancel (2)
 *
 * In the case where P is disabled we only need 1 extra source:
 * 1/ {01} * Q : use Q to continue Q' calculation
 */
static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
{
	if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
		return dma_dev_to_maxpq(dma);
	else if (dmaf_p_disabled_continue(flags))
		return dma_dev_to_maxpq(dma) - 1;
	else if (dmaf_continue(flags))
		return dma_dev_to_maxpq(dma) - 3;
	BUG();
}

static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg,
				      size_t dir_icg)
{
	if (inc) {
		if (dir_icg)
			return dir_icg;
		else if (sgl)
			return icg;
	}

return 0;
}

static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt,
					   struct data_chunk *chunk)
{
	return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,
				 chunk->icg, chunk->dst_icg);
}

static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt,
					   struct data_chunk *chunk)
{
	return dmaengine_get_icg(xt->src_inc, xt->src_sgl,
				 chunk->icg, chunk->src_icg);
}

/* --- public DMA engine API --- */

#ifdef CONFIG_DMA_ENGINE
void dmaengine_get(void);
void dmaengine_put(void);
#else
static inline void dmaengine_get(void)
{
}
static inline void dmaengine_put(void)
{
}
#endif

#ifdef CONFIG_ASYNC_TX_DMA
#define async_dmaengine_get()	dmaengine_get()
#define async_dmaengine_put()	dmaengine_put()
#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
#else
#define async_dma_find_channel(type) dma_find_channel(type)
#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
#else
static inline void async_dmaengine_get(void)
{
}
static inline void async_dmaengine_put(void)
{
}
static inline struct dma_chan *
async_dma_find_channel(enum dma_transaction_type type)
{
	return NULL;
}
#endif /* CONFIG_ASYNC_TX_DMA */
void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
				  struct dma_chan *chan);

static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
{
	tx->flags |= DMA_CTRL_ACK;
}

static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
{
	tx->flags &= ~DMA_CTRL_ACK;
}

static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
{
	return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
}

#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
static inline void
__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
{
	set_bit(tx_type, dstp->bits);
}

#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
static inline void
__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
{
	clear_bit(tx_type, dstp->bits);
}

#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
{
	bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
}

#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
static inline int
__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
{
	return test_bit(tx_type, srcp->bits);
}

#define for_each_dma_cap_mask(cap, mask) \
	for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)

/**
 * dma_async_issue_pending - flush pending transactions to HW
 * @chan: target DMA channel
 *
 * This allows drivers to push copies to HW in batches,
 * reducing MMIO writes where possible.
 */
static inline void dma_async_issue_pending(struct dma_chan *chan)
{
	chan->device->device_issue_pending(chan);
}

/**
 * dma_async_is_tx_complete - poll for transaction completion
 * @chan: DMA channel
 * @cookie: transaction identifier to check status of
 * @last: returns last completed cookie, can be NULL
 * @used: returns last issued cookie, can be NULL
 *
 * If @last and @used are passed in, upon return they reflect the driver
 * internal state and can be used with dma_async_is_complete() to check
 * the status of multiple cookies without re-checking hardware state.
 */
static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
	dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
{
	struct dma_tx_state state;
	enum dma_status status;

status = chan->device->device_tx_status(chan, cookie, &state);
	if (last)
		*last = state.last;
	if (used)
		*used = state.used;
	return status;
}

/**
 * dma_async_is_complete - test a cookie against chan state
 * @cookie: transaction identifier to test status of
 * @last_complete: last know completed transaction
 * @last_used: last cookie value handed out
 *
 * dma_async_is_complete() is used in dma_async_is_tx_complete()
 * the test logic is separated for lightweight testing of multiple cookies
 */
static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
			dma_cookie_t last_complete, dma_cookie_t last_used)
{
	if (last_complete <= last_used) {
		if ((cookie <= last_complete) || (cookie > last_used))
			return DMA_COMPLETE;
	} else {
		if ((cookie <= last_complete) && (cookie > last_used))
			return DMA_COMPLETE;
	}
	return DMA_IN_PROGRESS;
}

static inline void
dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
{
	if (st) {
		st->last = last;
		st->used = used;
		st->residue = residue;
	}
}

#ifdef CONFIG_DMA_ENGINE
struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
void dma_issue_pending_all(void);
struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
					dma_filter_fn fn, void *fn_param);
struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);

struct dma_chan *dma_request_chan(struct device *dev, const char *name);
struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);

void dma_release_channel(struct dma_chan *chan);
int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
#else
static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
{
	return NULL;
}
static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
{
	return DMA_COMPLETE;
}
static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
{
	return DMA_COMPLETE;
}
static inline void dma_issue_pending_all(void)
{
}
static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
					      dma_filter_fn fn, void *fn_param)
{
	return NULL;
}
static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
							 const char *name)
{
	return NULL;
}
static inline struct dma_chan *dma_request_chan(struct device *dev,
						const char *name)
{
	return ERR_PTR(-ENODEV);
}
static inline struct dma_chan *dma_request_chan_by_mask(
						const dma_cap_mask_t *mask)
{
	return ERR_PTR(-ENODEV);
}
static inline void dma_release_channel(struct dma_chan *chan)
{
}
static inline int dma_get_slave_caps(struct dma_chan *chan,
				     struct dma_slave_caps *caps)
{
	return -ENXIO;
}
#endif

#define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name)

static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx)
{
	struct dma_slave_caps caps;
	int ret;

ret = dma_get_slave_caps(tx->chan, &caps);
	if (ret)
		return ret;

if (caps.descriptor_reuse) {
		tx->flags |= DMA_CTRL_REUSE;
		return 0;
	} else {
		return -EPERM;
	}
}

static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx)
{
	tx->flags &= ~DMA_CTRL_REUSE;
}

static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx)
{
	return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;
}

static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc)
{
	/* this is supported for reusable desc, so check that */
	if (dmaengine_desc_test_reuse(desc))
		return desc->desc_free(desc);
	else
		return -EPERM;
}

/* --- DMA device --- */

int dma_async_device_register(struct dma_device *device);
void dma_async_device_unregister(struct dma_device *device);
void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
struct dma_chan *dma_get_any_slave_channel(struct dma_device *device);
#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
#define dma_request_slave_channel_compat(mask, x, y, dev, name) \
	__dma_request_slave_channel_compat(&(mask), x, y, dev, name)

static inline struct dma_chan
*__dma_request_slave_channel_compat(const dma_cap_mask_t *mask,
				  dma_filter_fn fn, void *fn_param,
				  struct device *dev, const char *name)
{
	struct dma_chan *chan;

chan = dma_request_slave_channel(dev, name);
	if (chan)
		return chan;

if (!fn || !fn_param)
		return NULL;

return __dma_request_channel(mask, fn, fn_param);
}
#endif /* DMAENGINE_H */