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05/09/2024 07:14:16 AM
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ad7877.h
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adi_spi3.h
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ads7846.h
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at73c213.h
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at86rf230.h
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cc2520.h
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corgi_lcd.h
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ds1305.h
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eeprom.h
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flash.h
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ifx_modem.h
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l4f00242t03.h
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libertas_spi.h
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lms283gf05.h
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max7301.h
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mc33880.h
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mcp23s08.h
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mmc_spi.h
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mxs-spi.h
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pxa2xx_spi.h
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rspi.h
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s3c24xx.h
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sh_hspi.h
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sh_msiof.h
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spi-fsl-dspi.h
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spi.h
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spi_bitbang.h
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spi_gpio.h
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spi_oc_tiny.h
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tdo24m.h
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tle62x0.h
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xilinx_spi.h
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Editing: eeprom.h
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/* SPDX-License-Identifier: GPL-2.0 */ #ifndef __LINUX_SPI_EEPROM_H #define __LINUX_SPI_EEPROM_H #include <linux/memory.h> /* * Put one of these structures in platform_data for SPI EEPROMS handled * by the "at25" driver. On SPI, most EEPROMS understand the same core * command set. If you need to support EEPROMs that don't yet fit, add * flags to support those protocol options. These values all come from * the chip datasheets. */ struct spi_eeprom { u32 byte_len; char name[10]; u16 page_size; /* for writes */ u16 flags; #define EE_ADDR1 0x0001 /* 8 bit addrs */ #define EE_ADDR2 0x0002 /* 16 bit addrs */ #define EE_ADDR3 0x0004 /* 24 bit addrs */ #define EE_READONLY 0x0008 /* disallow writes */ /* * Certain EEPROMS have a size that is larger than the number of address * bytes would allow (e.g. like M95040 from ST that has 512 Byte size * but uses only one address byte (A0 to A7) for addressing.) For * the extra address bit (A8, A16 or A24) bit 3 of the instruction byte * is used. This instruction bit is normally defined as don't care for * other AT25 like chips. */ #define EE_INSTR_BIT3_IS_ADDR 0x0010 void *context; }; #endif /* __LINUX_SPI_EEPROM_H */