OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:12 AM	rwxr-xr-x
📄 Kbuild	658 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	2.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin-global.h	2.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin-lq035q1.h	868 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin5xx_spi.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_can.h	36.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_dma.h	5.46 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_pfmon.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_ppi.h	9.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_sdh.h	7.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_serial.h	17.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_simple_timer.h	949 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_sport.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_sport3.h	5.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_twi.h	6.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfin_watchdog.h	696 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bfrom.h	3.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	3.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 blackfin.h	1.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	1.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	3.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cdef_LPBlackfin.h	18.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	899 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clkdev.h	318 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocks.h	1.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 context.S	5.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cplb.h	4.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cplbinit.h	1.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu.h	443 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 def_LPBlackfin.h	28.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	917 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	9.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dpmc.h	18.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 early_printk.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	4.88 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 entry.h	5.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exec.h	37 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixed_code.h	806 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 flat.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gpio.h	5.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gptimers.h	8.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	301 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	1.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipipe.h	5.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipipe_base.h	2.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	879 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_handler.h	1.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	7.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	3.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 l1layout.h	879 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	205 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mem_init.h	13.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mem_map.h	1.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	713 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	5.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	410 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nand.h	895 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nmi.h	195 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	546 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_offset.h	192 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	310 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pda.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	23 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pm.h	590 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 portmux.h	16.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	3.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pseudo_instructions.h	391 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reboot.h	446 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rwlock.h	142 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 scb.h	445 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 segment.h	226 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	1.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	495 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	997 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	2.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 time.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	477 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	481 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	88 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 trace.h	2.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	4.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	5.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	523 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	29 bytes	01/28/2018 09:20:33 PM	rw-r--r--

Editing: bfin_twi.h

/*
 * bfin_twi.h - interface to Blackfin TWIs
 *
 * Copyright 2005-2014 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#ifndef __ASM_BFIN_TWI_H__
#define __ASM_BFIN_TWI_H__

#include <asm/blackfin.h>
#include <linux/types.h>
#include <linux/i2c.h>

/*
 * ADI twi registers layout
 */
struct bfin_twi_regs {
	u16 clkdiv;
	u16 dummy1;
	u16 control;
	u16 dummy2;
	u16 slave_ctl;
	u16 dummy3;
	u16 slave_stat;
	u16 dummy4;
	u16 slave_addr;
	u16 dummy5;
	u16 master_ctl;
	u16 dummy6;
	u16 master_stat;
	u16 dummy7;
	u16 master_addr;
	u16 dummy8;
	u16 int_stat;
	u16 dummy9;
	u16 int_mask;
	u16 dummy10;
	u16 fifo_ctl;
	u16 dummy11;
	u16 fifo_stat;
	u16 dummy12;
	u32 __pad[20];
	u16 xmt_data8;
	u16 dummy13;
	u16 xmt_data16;
	u16 dummy14;
	u16 rcv_data8;
	u16 dummy15;
	u16 rcv_data16;
	u16 dummy16;
};

struct bfin_twi_iface {
	int			irq;
	spinlock_t		lock;
	char			read_write;
	u8			command;
	u8			*transPtr;
	int			readNum;
	int			writeNum;
	int			cur_mode;
	int			manual_stop;
	int			result;
	struct i2c_adapter	adap;
	struct completion	complete;
	struct i2c_msg		*pmsg;
	int			msg_num;
	int			cur_msg;
	u16			saved_clkdiv;
	u16			saved_control;
	struct bfin_twi_regs __iomem *regs_base;
};

/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ********************/
/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  ) */
#define	CLKLOW(x)	((x) & 0xFF)	/* Periods Clock Is Held Low */
#define CLKHI(y)	(((y)&0xFF)<<0x8) /* Periods Before New Clock Low */

/* TWI_PRESCALE Masks */
#define	PRESCALE	0x007F	/* SCLKs Per Internal Time Reference (10MHz) */
#define	TWI_ENA		0x0080	/* TWI Enable */
#define	SCCB		0x0200	/* SCCB Compatibility Enable */

/* TWI_SLAVE_CTL Masks */
#define	SEN		0x0001	/* Slave Enable */
#define	SADD_LEN	0x0002	/* Slave Address Length */
#define	STDVAL		0x0004	/* Slave Transmit Data Valid */
#define	NAK		0x0008	/* NAK Generated At Conclusion Of Transfer */
#define	GEN		0x0010	/* General Call Address Matching Enabled */

/* TWI_SLAVE_STAT Masks	*/
#define	SDIR		0x0001	/* Slave Transfer Direction (RX/TX*) */
#define GCALL		0x0002	/* General Call Indicator */

/* TWI_MASTER_CTL Masks	*/
#define	MEN		0x0001	/* Master Mode Enable          */
#define	MADD_LEN	0x0002	/* Master Address Length       */
#define	MDIR		0x0004	/* Master Transmit Direction (RX/TX*) */
#define	FAST		0x0008	/* Use Fast Mode Timing Specs  */
#define	STOP		0x0010	/* Issue Stop Condition        */
#define	RSTART		0x0020	/* Repeat Start or Stop* At End Of Transfer */
#define	DCNT		0x3FC0	/* Data Bytes To Transfer      */
#define	SDAOVR		0x4000	/* Serial Data Override        */
#define	SCLOVR		0x8000	/* Serial Clock Override       */

/* TWI_MASTER_STAT Masks */
#define	MPROG		0x0001	/* Master Transfer In Progress */
#define	LOSTARB		0x0002	/* Lost Arbitration Indicator (Xfer Aborted) */
#define	ANAK		0x0004	/* Address Not Acknowledged    */
#define	DNAK		0x0008	/* Data Not Acknowledged       */
#define	BUFRDERR	0x0010	/* Buffer Read Error           */
#define	BUFWRERR	0x0020	/* Buffer Write Error          */
#define	SDASEN		0x0040	/* Serial Data Sense           */
#define	SCLSEN		0x0080	/* Serial Clock Sense          */
#define	BUSBUSY		0x0100	/* Bus Busy Indicator          */

/* TWI_INT_SRC and TWI_INT_ENABLE Masks	*/
#define	SINIT		0x0001	/* Slave Transfer Initiated    */
#define	SCOMP		0x0002	/* Slave Transfer Complete     */
#define	SERR		0x0004	/* Slave Transfer Error        */
#define	SOVF		0x0008	/* Slave Overflow              */
#define	MCOMP		0x0010	/* Master Transfer Complete    */
#define	MERR		0x0020	/* Master Transfer Error       */
#define	XMTSERV		0x0040	/* Transmit FIFO Service       */
#define	RCVSERV		0x0080	/* Receive FIFO Service        */

/* TWI_FIFO_CTRL Masks */
#define	XMTFLUSH	0x0001	/* Transmit Buffer Flush                 */
#define	RCVFLUSH	0x0002	/* Receive Buffer Flush                  */
#define	XMTINTLEN	0x0004	/* Transmit Buffer Interrupt Length      */
#define	RCVINTLEN	0x0008	/* Receive Buffer Interrupt Length       */

/* TWI_FIFO_STAT Masks */
#define	XMTSTAT		0x0003	/* Transmit FIFO Status                  */
#define	XMT_EMPTY	0x0000	/* Transmit FIFO Empty                   */
#define	XMT_HALF	0x0001	/* Transmit FIFO Has 1 Byte To Write     */
#define	XMT_FULL	0x0003	/* Transmit FIFO Full (2 Bytes To Write) */

#define	RCVSTAT		0x000C	/* Receive FIFO Status                   */
#define	RCV_EMPTY	0x0000	/* Receive FIFO Empty                    */
#define	RCV_HALF	0x0004	/* Receive FIFO Has 1 Byte To Read       */
#define	RCV_FULL	0x000C	/* Receive FIFO Full (2 Bytes To Read)   */

#define DEFINE_TWI_REG(reg_name, reg) \
static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
	{ return bfin_read16(&iface->regs_base->reg); } \
static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
	{ bfin_write16(&iface->regs_base->reg, v); }

DEFINE_TWI_REG(CLKDIV, clkdiv)
DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
DEFINE_TWI_REG(MASTER_CTL, master_ctl)
DEFINE_TWI_REG(MASTER_STAT, master_stat)
DEFINE_TWI_REG(MASTER_ADDR, master_addr)
DEFINE_TWI_REG(INT_STAT, int_stat)
DEFINE_TWI_REG(INT_MASK, int_mask)
DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
#if !ANOMALY_16000030
DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
#else
static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
{
	u16 ret;
	unsigned long flags;

flags = hard_local_irq_save();
	ret = bfin_read16(&iface->regs_base->rcv_data8);
	hard_local_irq_restore(flags);

return ret;
}

static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
{
	u16 ret;
	unsigned long flags;

flags = hard_local_irq_save();
	ret = bfin_read16(&iface->regs_base->rcv_data16);
	hard_local_irq_restore(flags);

return ret;
}
#endif

static inline u16 read_FIFO_CTL(struct bfin_twi_iface *iface)
{
	return bfin_read16(&iface->regs_base->fifo_ctl);
}

static inline void write_FIFO_CTL(struct bfin_twi_iface *iface, u16 v)
{
	bfin_write16(&iface->regs_base->fifo_ctl, v);
	SSYNC();
}

static inline u16 read_CONTROL(struct bfin_twi_iface *iface)
{
	return bfin_read16(&iface->regs_base->control);
}

static inline void write_CONTROL(struct bfin_twi_iface *iface, u16 v)
{
	SSYNC();
	bfin_write16(&iface->regs_base->control, v);
}
#endif