OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 88pm80x.h	9.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 88pm860x.h	13.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 aat2870.h	4.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ab3100.h	4.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 abx500	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 abx500.h	11.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ac100.h	6.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 adp5520.h	8.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 altera-a10sr.h	3.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 arizona	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 as3711.h	2.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 as3722.h	15.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asic3.h	12.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atmel-hlcdc.h	2.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 axp20x.h	16.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bcm590xx.h	831 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bd9571mwv.h	3.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 core.h	4.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cros_ec.h	10.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cros_ec_commands.h	84.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cros_ec_lpc_mec.h	2.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cros_ec_lpc_reg.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 da8xx-cfgchip.h	7.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 da903x.h	7.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 da9052	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📁 da9055	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📁 da9062	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📁 da9063	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📁 da9150	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 davinci_voicecodec.h	3.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 db8500-prcmu.h	21.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dbx500-prcmu.h	14.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dln2.h	3.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dm355evm_msp.h	2.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ds1wm.h	817 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ezx-pcap.h	7.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hi6421-pmic.h	1.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hi655x-pmic.h	2.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 htc-pasic3.h	1.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 imx25-tsadc.h	4.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_msic.h	15.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 intel_soc_pmic.h	1.17 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 intel_soc_pmic_bxtwc.h	2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipaq-micro.h	3.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 janz.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kempld.h	4.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lm3533.h	2.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lp3943.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lp873x.h	8.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lp87565.h	7.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lp8788-isink.h	1.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lp8788.h	8.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lpc_ich.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max14577-private.h	15.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max14577.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max77620.h	10.87 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 max77686-private.h	13.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max77686.h	2.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max77693-common.h	1.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max77693-private.h	17.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max77693.h	2.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max77843-private.h	15.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max8907.h	7.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max8925.h	7.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max8997-private.h	12.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max8997.h	6.04 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 max8998-private.h	5.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 max8998.h	3.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc13783.h	2.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc13892.h	938 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc13xxx.h	7.65 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mcp.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 menelaus.h	1.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 motorola-cpcap.h	12.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 mt6323	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📁 mt6397	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 mxs-lradc.h	6.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 palmas.h	149.07 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 pcf50633	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 qcom_rpm.h	293 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rc5t583.h	9.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rdc321x.h	591 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 retu.h	723 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rk808.h	12.51 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rn5t618.h	7.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rt5033-private.h	7.84 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 rt5033.h	1.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 samsung	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 si476x-core.h	15.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 si476x-platform.h	6.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 si476x-reports.h	4.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sky81452.h	990 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smsc.h	2.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sta2x11-mfd.h	18.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stm32-lptimer.h	1.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stm32-timers.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stmpe.h	3.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stw481x.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sun4i-gpadc.h	3.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 syscon	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 syscon.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 t7l66xb.h	771 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 tc3589x.h	3.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tc6387xb.h	516 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tc6393xb.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ti-lmu-register.h	7.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ti-lmu.h	1.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ti_am335x_tscadc.h	5.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tmio.h	4.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tps6105x.h	3.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tps65010.h	6.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tps6507x.h	4.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tps65086.h	3.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tps65090.h	4.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tps65217.h	8.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tps65218.h	7.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tps6586x.h	2.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tps65910.h	30.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tps65912.h	9.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tps68470.h	3.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tps80031.h	19.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 twl.h	25.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 twl4030-audio.h	8.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 twl6040.h	7.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ucb1x00.h	6.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 viperboard.h	2.95 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 wl1273-core.h	8.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 wm831x	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📁 wm8350	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 wm8400-audio.h	69.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 wm8400-private.h	57.98 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 wm8400.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 wm8994	-	11/17/2022 06:42:23 AM	rwxr-xr-x
📄 wm97xx.h	576 bytes	01/28/2018 09:20:33 PM	rw-r--r--

Editing: rt5033-private.h

/*
 * MFD core driver for Richtek RT5033
 *
 * Copyright (C) 2014 Samsung Electronics, Co., Ltd.
 * Author: Beomho Seo <beomho.seo@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published bythe Free Software Foundation.
 */

#ifndef __RT5033_PRIVATE_H__
#define __RT5033_PRIVATE_H__

enum rt5033_reg {
	RT5033_REG_CHG_STAT		= 0x00,
	RT5033_REG_CHG_CTRL1		= 0x01,
	RT5033_REG_CHG_CTRL2		= 0x02,
	RT5033_REG_DEVICE_ID		= 0x03,
	RT5033_REG_CHG_CTRL3		= 0x04,
	RT5033_REG_CHG_CTRL4		= 0x05,
	RT5033_REG_CHG_CTRL5		= 0x06,
	RT5033_REG_RT_CTRL0		= 0x07,
	RT5033_REG_CHG_RESET		= 0x08,
	/* Reserved 0x09~0x18 */
	RT5033_REG_RT_CTRL1		= 0x19,
	/* Reserved 0x1A~0x20 */
	RT5033_REG_FLED_FUNCTION1	= 0x21,
	RT5033_REG_FLED_FUNCTION2	= 0x22,
	RT5033_REG_FLED_STROBE_CTRL1	= 0x23,
	RT5033_REG_FLED_STROBE_CTRL2	= 0x24,
	RT5033_REG_FLED_CTRL1		= 0x25,
	RT5033_REG_FLED_CTRL2		= 0x26,
	RT5033_REG_FLED_CTRL3		= 0x27,
	RT5033_REG_FLED_CTRL4		= 0x28,
	RT5033_REG_FLED_CTRL5		= 0x29,
	/* Reserved 0x2A~0x40 */
	RT5033_REG_CTRL			= 0x41,
	RT5033_REG_BUCK_CTRL		= 0x42,
	RT5033_REG_LDO_CTRL		= 0x43,
	/* Reserved 0x44~0x46 */
	RT5033_REG_MANUAL_RESET_CTRL	= 0x47,
	/* Reserved 0x48~0x5F */
	RT5033_REG_CHG_IRQ1		= 0x60,
	RT5033_REG_CHG_IRQ2		= 0x61,
	RT5033_REG_CHG_IRQ3		= 0x62,
	RT5033_REG_CHG_IRQ1_CTRL	= 0x63,
	RT5033_REG_CHG_IRQ2_CTRL	= 0x64,
	RT5033_REG_CHG_IRQ3_CTRL	= 0x65,
	RT5033_REG_LED_IRQ_STAT		= 0x66,
	RT5033_REG_LED_IRQ_CTRL		= 0x67,
	RT5033_REG_PMIC_IRQ_STAT	= 0x68,
	RT5033_REG_PMIC_IRQ_CTRL	= 0x69,
	RT5033_REG_SHDN_CTRL		= 0x6A,
	RT5033_REG_OFF_EVENT		= 0x6B,

RT5033_REG_END,
};

/* RT5033 Charger state register */
#define RT5033_CHG_STAT_MASK		0x20
#define RT5033_CHG_STAT_DISCHARGING	0x00
#define RT5033_CHG_STAT_FULL		0x10
#define RT5033_CHG_STAT_CHARGING	0x20
#define RT5033_CHG_STAT_NOT_CHARGING	0x30
#define RT5033_CHG_STAT_TYPE_MASK	0x60
#define RT5033_CHG_STAT_TYPE_PRE	0x20
#define RT5033_CHG_STAT_TYPE_FAST	0x60

/* RT5033 CHGCTRL1 register */
#define RT5033_CHGCTRL1_IAICR_MASK	0xe0
#define RT5033_CHGCTRL1_MODE_MASK	0x01

/* RT5033 CHGCTRL2 register */
#define RT5033_CHGCTRL2_CV_MASK		0xfc

/* RT5033 CHGCTRL3 register */
#define RT5033_CHGCTRL3_CFO_EN_MASK	0x40
#define RT5033_CHGCTRL3_TIMER_MASK	0x38
#define RT5033_CHGCTRL3_TIMER_EN_MASK	0x01

/* RT5033 CHGCTRL4 register */
#define RT5033_CHGCTRL4_EOC_MASK	0x07
#define RT5033_CHGCTRL4_IPREC_MASK	0x18

/* RT5033 CHGCTRL5 register */
#define RT5033_CHGCTRL5_VPREC_MASK	0x0f
#define RT5033_CHGCTRL5_ICHG_MASK	0xf0
#define RT5033_CHGCTRL5_ICHG_SHIFT	0x04
#define RT5033_CHG_MAX_CURRENT		0x0d

/* RT5033 RT CTRL1 register */
#define RT5033_RT_CTRL1_UUG_MASK	0x02
#define RT5033_RT_HZ_MASK		0x01

/* RT5033 control register */
#define RT5033_CTRL_FCCM_BUCK_MASK		0x00
#define RT5033_CTRL_BUCKOMS_MASK		0x01
#define RT5033_CTRL_LDOOMS_MASK			0x02
#define RT5033_CTRL_SLDOOMS_MASK		0x03
#define RT5033_CTRL_EN_BUCK_MASK		0x04
#define RT5033_CTRL_EN_LDO_MASK			0x05
#define RT5033_CTRL_EN_SAFE_LDO_MASK		0x06
#define RT5033_CTRL_LDO_SLEEP_MASK		0x07

/* RT5033 BUCK control register */
#define RT5033_BUCK_CTRL_MASK			0x1f

/* RT5033 LDO control register */
#define RT5033_LDO_CTRL_MASK			0x1f

/* RT5033 charger property - model, manufacturer */

#define RT5033_CHARGER_MODEL	"RT5033WSC Charger"
#define RT5033_MANUFACTURER	"Richtek Technology Corporation"

/*
 * RT5033 charger fast-charge current lmits (as in CHGCTRL1 register),
 * AICR mode limits the input current for example,
 * the AIRC 100 mode limits the input current to 100 mA.
 */
#define RT5033_AICR_100_MODE			0x20
#define RT5033_AICR_500_MODE			0x40
#define RT5033_AICR_700_MODE			0x60
#define RT5033_AICR_900_MODE			0x80
#define RT5033_AICR_1500_MODE			0xc0
#define RT5033_AICR_2000_MODE			0xe0
#define RT5033_AICR_MODE_MASK			0xe0

/* RT5033 use internal timer need to set time */
#define RT5033_FAST_CHARGE_TIMER4		0x00
#define RT5033_FAST_CHARGE_TIMER6		0x01
#define RT5033_FAST_CHARGE_TIMER8		0x02
#define RT5033_FAST_CHARGE_TIMER9		0x03
#define RT5033_FAST_CHARGE_TIMER12		0x04
#define RT5033_FAST_CHARGE_TIMER14		0x05
#define RT5033_FAST_CHARGE_TIMER16		0x06

#define RT5033_INT_TIMER_ENABLE			0x01

/* RT5033 charger termination enable mask */
#define RT5033_TE_ENABLE_MASK			0x08

/*
 * RT5033 charger opa mode. RT50300 have two opa mode charger mode
 * and boost mode for OTG
 */

#define RT5033_CHARGER_MODE			0x00
#define RT5033_BOOST_MODE			0x01

/* RT5033 charger termination enable */
#define RT5033_TE_ENABLE			0x08

/* RT5033 charger CFO enable */
#define RT5033_CFO_ENABLE			0x40

/* RT5033 charger constant charge voltage (as in CHGCTRL2 register), uV */
#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MIN	3650000U
#define RT5033_CHARGER_CONST_VOLTAGE_STEP_NUM   25000U
#define RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MAX	4400000U

/* RT5033 charger pre-charge current limits (as in CHGCTRL4 register), uA */
#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MIN	350000U
#define RT5033_CHARGER_PRE_CURRENT_STEP_NUM	100000U
#define RT5033_CHARGER_PRE_CURRENT_LIMIT_MAX	650000U

/* RT5033 charger fast-charge current (as in CHGCTRL5 register), uA */
#define RT5033_CHARGER_FAST_CURRENT_MIN		700000U
#define RT5033_CHARGER_FAST_CURRENT_STEP_NUM	100000U
#define RT5033_CHARGER_FAST_CURRENT_MAX		2000000U

/*
 * RT5033 charger const-charge end of charger current (
 * as in CHGCTRL4 register), uA
 */
#define RT5033_CHARGER_EOC_MIN			150000U
#define RT5033_CHARGER_EOC_REF			300000U
#define RT5033_CHARGER_EOC_STEP_NUM1		50000U
#define RT5033_CHARGER_EOC_STEP_NUM2		100000U
#define RT5033_CHARGER_EOC_MAX			600000U

/*
 * RT5033 charger pre-charge threshold volt limits
 * (as in CHGCTRL5 register), uV
 */

#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MIN	2300000U
#define RT5033_CHARGER_PRE_THRESHOLD_STEP_NUM	100000U
#define RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MAX	3800000U

/*
 * RT5033 charger enable UUG, If UUG enable MOS auto control by H/W charger
 * circuit.
 */
#define RT5033_CHARGER_UUG_ENABLE		0x02

/* RT5033 charger High impedance mode */
#define RT5033_CHARGER_HZ_DISABLE		0x00
#define RT5033_CHARGER_HZ_ENABLE		0x01

/* RT5033 regulator BUCK output voltage uV */
#define RT5033_REGULATOR_BUCK_VOLTAGE_MIN		1000000U
#define RT5033_REGULATOR_BUCK_VOLTAGE_MAX		3000000U
#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP		100000U
#define RT5033_REGULATOR_BUCK_VOLTAGE_STEP_NUM		21

/* RT5033 regulator LDO output voltage uV */
#define RT5033_REGULATOR_LDO_VOLTAGE_MIN		1200000U
#define RT5033_REGULATOR_LDO_VOLTAGE_MAX		3000000U
#define RT5033_REGULATOR_LDO_VOLTAGE_STEP		100000U
#define RT5033_REGULATOR_LDO_VOLTAGE_STEP_NUM		19

/* RT5033 regulator SAFE LDO output voltage uV */
#define RT5033_REGULATOR_SAFE_LDO_VOLTAGE		4900000U

enum rt5033_fuel_reg {
	RT5033_FUEL_REG_OCV_H		= 0x00,
	RT5033_FUEL_REG_OCV_L		= 0x01,
	RT5033_FUEL_REG_VBAT_H		= 0x02,
	RT5033_FUEL_REG_VBAT_L		= 0x03,
	RT5033_FUEL_REG_SOC_H		= 0x04,
	RT5033_FUEL_REG_SOC_L		= 0x05,
	RT5033_FUEL_REG_CTRL_H		= 0x06,
	RT5033_FUEL_REG_CTRL_L		= 0x07,
	RT5033_FUEL_REG_CRATE		= 0x08,
	RT5033_FUEL_REG_DEVICE_ID	= 0x09,
	RT5033_FUEL_REG_AVG_VOLT_H	= 0x0A,
	RT5033_FUEL_REG_AVG_VOLT_L	= 0x0B,
	RT5033_FUEL_REG_CONFIG_H	= 0x0C,
	RT5033_FUEL_REG_CONFIG_L	= 0x0D,
	/* Reserved 0x0E~0x0F */
	RT5033_FUEL_REG_IRQ_CTRL	= 0x10,
	RT5033_FUEL_REG_IRQ_FLAG	= 0x11,
	RT5033_FUEL_VMIN		= 0x12,
	RT5033_FUEL_SMIN		= 0x13,
	/* Reserved 0x14~0x1F */
	RT5033_FUEL_VGCOMP1		= 0x20,
	RT5033_FUEL_VGCOMP2		= 0x21,
	RT5033_FUEL_VGCOMP3		= 0x22,
	RT5033_FUEL_VGCOMP4		= 0x23,
	/* Reserved 0x24~0xFD */
	RT5033_FUEL_MFA_H		= 0xFE,
	RT5033_FUEL_MFA_L		= 0xFF,

RT5033_FUEL_REG_END,
};

/* RT5033 fuel gauge battery present property */
#define RT5033_FUEL_BAT_PRESENT		0x02

/* RT5033 PMIC interrupts */
#define RT5033_PMIC_IRQ_BUCKOCP		2
#define RT5033_PMIC_IRQ_BUCKLV		3
#define RT5033_PMIC_IRQ_SAFELDOLV	4
#define RT5033_PMIC_IRQ_LDOLV		5
#define RT5033_PMIC_IRQ_OT		6
#define RT5033_PMIC_IRQ_VDDA_UV		7

#endif /* __RT5033_PRIVATE_H__ */