OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	491 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 agp.h	434 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 apb.h	1.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	727 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asmmacro.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	219 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic_32.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic_64.h	3.34 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 auxio.h	310 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 auxio_32.h	2.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 auxio_64.h	3.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 backoff.h	2.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	223 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier_32.h	160 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier_64.h	1.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bbc.h	9.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitext.h	631 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops.h	219 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops_32.h	2.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bitops_64.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 btext.h	145 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	588 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 bugs.h	404 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	649 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	373 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush_32.h	1.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush_64.h	2.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cachetlb_32.h	882 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 chafsr.h	9.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum_32.h	6.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum_64.h	4.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 chmctrl.h	7.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clock.h	231 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 clocksource.h	407 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	223 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg_32.h	2.4 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg_64.h	5.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 compat.h	6.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat_signal.h	565 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 contregs.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu_type.h	579 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpudata.h	378 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpudata_32.h	729 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpudata_64.h	1.13 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 current.h	991 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr.h	728 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcu.h	1.48 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay_32.h	907 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay_64.h	403 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	565 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	632 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	6.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ebus_dma.h	1.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ecc.h	4.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeprom.h	254 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	207 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf_32.h	3.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf_64.h	6.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 estate.h	2.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable_64.h	727 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fb.h	680 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fbio.h	2.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fhc.h	4.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	219 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy_32.h	9.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy_64.h	18.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fpumacro.h	710 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	800 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex_32.h	82 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex_64.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	223 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq_32.h	334 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq_64.h	417 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 head.h	211 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 head_32.h	2.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 head_64.h	2.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hibernate.h	421 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hvtramp.h	782 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	88 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hypervisor.h	110.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	2.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 idprom.h	656 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 intr_queue.h	794 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-unit.h	2.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	620 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_32.h	3.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io_64.h	10.66 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ioctls.h	358 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu_32.h	5.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu_64.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	207 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_32.h	526 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_64.h	3.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags_32.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags_64.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	219 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug_32.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug_64.h	393 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	1014 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	233 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ldc.h	4.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 leon.h	7.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 leon_amba.h	8.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 leon_pci.h	512 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 lsu.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 machines.h	1.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mbus.h	2.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	298 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc_32.h	699 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc_64.h	689 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mdesc.h	2.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 memctrl.h	311 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mman.h	304 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	207 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_32.h	209 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_64.h	3.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	239 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context_32.h	1.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context_64.h	4.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmzone.h	393 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 msi.h	774 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mxcc.h	4.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nmi.h	354 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ns87303.h	3.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 obio.h	6.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 openprom.h	7.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 oplib.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 oplib_32.h	5.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 oplib_64.h	8.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	274 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_32.h	3.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_64.h	4.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 parport.h	5.68 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pbm.h	1.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci.h	207 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_32.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_64.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pcic.h	5.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pcr.h	1.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu.h	219 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu_32.h	168 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu_64.h	515 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event.h	802 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	223 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc_32.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc_64.h	2.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	223 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable_32.h	11.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable_64.h	30.71 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtsrmmu.h	6.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pil.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	231 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor_32.h	3.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor_64.h	7.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 prom.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 psr.h	1.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	4.19 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 qrwlock.h	205 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 qspinlock.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ross.h	5.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sbi.h	3.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scratchpad.h	547 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	225 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	289 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	1.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfafsr.h	3.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfp-machine.h	239 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfp-machine_32.h	6.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sfp-machine_64.h	3.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam_32.h	253 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam_64.h	306 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sigcontext.h	2.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	835 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	207 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp_32.h	3.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp_64.h	1.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	349 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_32.h	4.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_64.h	409 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	549 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spitfire.h	9.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 stacktrace.h	166 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 starfire.h	418 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	1.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string_32.h	405 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 string_64.h	505 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sunbpp.h	3.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 swift.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	231 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to_32.h	3.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to_64.h	2.58 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 syscall.h	3.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscalls.h	307 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 termbits.h	198 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 termios.h	4.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	239 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info_32.h	3.66 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info_64.h	7.84 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timer.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 timer_32.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timer_64.h	2.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	215 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex_32.h	266 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 timex_64.h	423 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb.h	207 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb_32.h	520 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlb_64.h	913 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush_32.h	621 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush_64.h	1.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology_32.h	170 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology_64.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 trap_block.h	6.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 traps.h	577 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 tsb.h	12.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tsunami.h	1.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ttable.h	20.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 turbosparc.h	3.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	363 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess_32.h	8.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess_64.h	6.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unaligned.h	339 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 unistd.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 upa.h	3.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uprobes.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	102 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vaddrs.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	662 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vga.h	964 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 viking.h	8.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vio.h	11.81 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 visasm.h	1.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
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📄 xor_64.h	2.5 KB	01/28/2018 09:20:33 PM	rw-r--r--

Editing: tsb.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _SPARC64_TSB_H
#define _SPARC64_TSB_H

/* The sparc64 TSB is similar to the powerpc hashtables.  It's a
 * power-of-2 sized table of TAG/PTE pairs.  The cpu precomputes
 * pointers into this table for 8K and 64K page sizes, and also a
 * comparison TAG based upon the virtual address and context which
 * faults.
 *
 * TLB miss trap handler software does the actual lookup via something
 * of the form:
 *
 * 	ldxa		[%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
 * 	ldxa		[%g0] ASI_{D,I}MMU, %g6
 *	sllx		%g6, 22, %g6
 *	srlx		%g6, 22, %g6
 * 	ldda		[%g1] ASI_NUCLEUS_QUAD_LDD, %g4
 * 	cmp		%g4, %g6
 * 	bne,pn	%xcc, tsb_miss_{d,i}tlb
 * 	 mov		FAULT_CODE_{D,I}TLB, %g3
 * 	stxa		%g5, [%g0] ASI_{D,I}TLB_DATA_IN
 * 	retry
 *
 *
 * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
 * PTE.  The TAG is of the same layout as the TLB TAG TARGET mmu
 * register which is:
 *
 * -------------------------------------------------
 * |  -  |  CONTEXT |  -  |    VADDR bits 63:22    |
 * -------------------------------------------------
 *  63 61 60      48 47 42 41                     0
 *
 * But actually, since we use per-mm TSB's, we zero out the CONTEXT
 * field.
 *
 * Like the powerpc hashtables we need to use locking in order to
 * synchronize while we update the entries.  PTE updates need locking
 * as well.
 *
 * We need to carefully choose a lock bits for the TSB entry.  We
 * choose to use bit 47 in the tag.  Also, since we never map anything
 * at page zero in context zero, we use zero as an invalid tag entry.
 * When the lock bit is set, this forces a tag comparison failure.
 */

#define TSB_TAG_LOCK_BIT	47
#define TSB_TAG_LOCK_HIGH	(1 << (TSB_TAG_LOCK_BIT - 32))

#define TSB_TAG_INVALID_BIT	46
#define TSB_TAG_INVALID_HIGH	(1 << (TSB_TAG_INVALID_BIT - 32))

/* Some cpus support physical address quad loads.  We want to use
 * those if possible so we don't need to hard-lock the TSB mapping
 * into the TLB.  We encode some instruction patching in order to
 * support this.
 *
 * The kernel TSB is locked into the TLB by virtue of being in the
 * kernel image, so we don't play these games for swapper_tsb access.
 */
#ifndef __ASSEMBLY__
struct tsb_ldquad_phys_patch_entry {
	unsigned int	addr;
	unsigned int	sun4u_insn;
	unsigned int	sun4v_insn;
};
extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
	__tsb_ldquad_phys_patch_end;

struct tsb_phys_patch_entry {
	unsigned int	addr;
	unsigned int	insn;
};
extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
#endif
#define TSB_LOAD_QUAD(TSB, REG)	\
661:	ldda		[TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
	.section	.tsb_ldquad_phys_patch, "ax"; \
	.word		661b; \
	ldda		[TSB] ASI_QUAD_LDD_PHYS, REG; \
	ldda		[TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
	.previous

#define TSB_LOAD_TAG_HIGH(TSB, REG) \
661:	lduwa		[TSB] ASI_N, REG; \
	.section	.tsb_phys_patch, "ax"; \
	.word		661b; \
	lduwa		[TSB] ASI_PHYS_USE_EC, REG; \
	.previous

#define TSB_LOAD_TAG(TSB, REG) \
661:	ldxa		[TSB] ASI_N, REG; \
	.section	.tsb_phys_patch, "ax"; \
	.word		661b; \
	ldxa		[TSB] ASI_PHYS_USE_EC, REG; \
	.previous

#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
661:	casa		[TSB] ASI_N, REG1, REG2; \
	.section	.tsb_phys_patch, "ax"; \
	.word		661b; \
	casa		[TSB] ASI_PHYS_USE_EC, REG1, REG2; \
	.previous

#define TSB_CAS_TAG(TSB, REG1, REG2) \
661:	casxa		[TSB] ASI_N, REG1, REG2; \
	.section	.tsb_phys_patch, "ax"; \
	.word		661b; \
	casxa		[TSB] ASI_PHYS_USE_EC, REG1, REG2; \
	.previous

#define TSB_STORE(ADDR, VAL) \
661:	stxa		VAL, [ADDR] ASI_N; \
	.section	.tsb_phys_patch, "ax"; \
	.word		661b; \
	stxa		VAL, [ADDR] ASI_PHYS_USE_EC; \
	.previous

#define TSB_LOCK_TAG(TSB, REG1, REG2)	\
99:	TSB_LOAD_TAG_HIGH(TSB, REG1);	\
	sethi	%hi(TSB_TAG_LOCK_HIGH), REG2;\
	andcc	REG1, REG2, %g0;	\
	bne,pn	%icc, 99b;		\
	 nop;				\
	TSB_CAS_TAG_HIGH(TSB, REG1, REG2);	\
	cmp	REG1, REG2;		\
	bne,pn	%icc, 99b;		\
	 nop;				\

#define TSB_WRITE(TSB, TTE, TAG) \
	add	TSB, 0x8, TSB;   \
	TSB_STORE(TSB, TTE);     \
	sub	TSB, 0x8, TSB;   \
	TSB_STORE(TSB, TAG);

/* Do a kernel page table walk.  Leaves valid PTE value in
	 * REG1.  Jumps to FAIL_LABEL on early page table walk
	 * termination.  VADDR will not be clobbered, but REG2 will.
	 *
	 * There are two masks we must apply to propagate bits from
	 * the virtual address into the PTE physical address field
	 * when dealing with huge pages.  This is because the page
	 * table boundaries do not match the huge page size(s) the
	 * hardware supports.
	 *
	 * In these cases we propagate the bits that are below the
	 * page table level where we saw the huge page mapping, but
	 * are still within the relevant physical bits for the huge
	 * page size in question.  So for PMD mappings (which fall on
	 * bit 23, for 8MB per PMD) we must propagate bit 22 for a
	 * 4MB huge page.  For huge PUDs (which fall on bit 33, for
	 * 8GB per PUD), we have to accommodate 256MB and 2GB huge
	 * pages.  So for those we propagate bits 32 to 28.
	 */
#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL)	\
	sethi		%hi(swapper_pg_dir), REG1; \
	or		REG1, %lo(swapper_pg_dir), REG1; \
	sllx		VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
	andn		REG2, 0x7, REG2; \
	ldx		[REG1 + REG2], REG1; \
	brz,pn		REG1, FAIL_LABEL; \
	 sllx		VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \
	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
	andn		REG2, 0x7, REG2; \
	ldxa		[REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
	brz,pn		REG1, FAIL_LABEL; \
	sethi		%uhi(_PAGE_PUD_HUGE), REG2; \
	brz,pn		REG1, FAIL_LABEL; \
	 sllx		REG2, 32, REG2; \
	andcc		REG1, REG2, %g0; \
	sethi		%hi(0xf8000000), REG2; \
	bne,pt		%xcc, 697f; \
	 sllx		REG2, 1, REG2; \
	sllx		VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
	andn		REG2, 0x7, REG2; \
	ldxa		[REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
	sethi		%uhi(_PAGE_PMD_HUGE), REG2; \
	brz,pn		REG1, FAIL_LABEL; \
	 sllx		REG2, 32, REG2; \
	andcc		REG1, REG2, %g0; \
	be,pn		%xcc, 698f; \
	 sethi		%hi(0x400000), REG2; \
697:	brgez,pn	REG1, FAIL_LABEL; \
	 andn		REG1, REG2, REG1; \
	and		VADDR, REG2, REG2; \
	ba,pt		%xcc, 699f; \
	 or		REG1, REG2, REG1; \
698:	sllx		VADDR, 64 - PMD_SHIFT, REG2; \
	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
	andn		REG2, 0x7, REG2; \
	ldxa		[REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
	brgez,pn	REG1, FAIL_LABEL; \
	 nop; \
699:

/* PUD has been loaded into REG1, interpret the value, seeing
	 * if it is a HUGE PUD or a normal one.  If it is not valid
	 * then jump to FAIL_LABEL.  If it is a HUGE PUD, and it
	 * translates to a valid PTE, branch to PTE_LABEL.
	 *
	 * We have to propagate bits [32:22] from the virtual address
	 * to resolve at 4M granularity.
	 */
#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
#define USER_PGTABLE_CHECK_PUD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
700:	ba 700f;					\
	 nop;						\
	.section	.pud_huge_patch, "ax";		\
	.word		700b;				\
	nop;						\
	.previous;					\
	brz,pn		REG1, FAIL_LABEL;		\
	 sethi		%uhi(_PAGE_PUD_HUGE), REG2;	\
	sllx		REG2, 32, REG2;			\
	andcc		REG1, REG2, %g0;		\
	be,pt		%xcc, 700f;			\
	 sethi		%hi(0xffe00000), REG2;		\
	sllx		REG2, 1, REG2;			\
	brgez,pn	REG1, FAIL_LABEL;		\
	 andn		REG1, REG2, REG1;		\
	and		VADDR, REG2, REG2;		\
	brlz,pt		REG1, PTE_LABEL;		\
	 or		REG1, REG2, REG1;		\
700:
#else
#define USER_PGTABLE_CHECK_PUD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
	brz,pn		REG1, FAIL_LABEL; \
	 nop;
#endif

/* PMD has been loaded into REG1, interpret the value, seeing
	 * if it is a HUGE PMD or a normal one.  If it is not valid
	 * then jump to FAIL_LABEL.  If it is a HUGE PMD, and it
	 * translates to a valid PTE, branch to PTE_LABEL.
	 *
	 * We have to propagate the 4MB bit of the virtual address
	 * because we are fabricating 8MB pages using 4MB hw pages.
	 */
#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
#define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
	brz,pn		REG1, FAIL_LABEL;		\
	 sethi		%uhi(_PAGE_PMD_HUGE), REG2;	\
	sllx		REG2, 32, REG2;			\
	andcc		REG1, REG2, %g0;		\
	be,pt		%xcc, 700f;			\
	 sethi		%hi(4 * 1024 * 1024), REG2;	\
	brgez,pn	REG1, FAIL_LABEL;		\
	 andn		REG1, REG2, REG1;		\
	and		VADDR, REG2, REG2;		\
	brlz,pt		REG1, PTE_LABEL;		\
	 or		REG1, REG2, REG1;		\
700:
#else
#define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
	brz,pn		REG1, FAIL_LABEL; \
	 nop;
#endif

/* Do a user page table walk in MMU globals.  Leaves final,
	 * valid, PTE value in REG1.  Jumps to FAIL_LABEL on early
	 * page table walk termination or if the PTE is not valid.
	 *
	 * Physical base of page tables is in PHYS_PGD which will not
	 * be modified.
	 *
	 * VADDR will not be clobbered, but REG1 and REG2 will.
	 */
#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL)	\
	sllx		VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
	andn		REG2, 0x7, REG2; \
	ldxa		[PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
	brz,pn		REG1, FAIL_LABEL; \
	 sllx		VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \
	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
	andn		REG2, 0x7, REG2; \
	ldxa		[REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
	USER_PGTABLE_CHECK_PUD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, 800f) \
	brz,pn		REG1, FAIL_LABEL; \
	 sllx		VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
	andn		REG2, 0x7, REG2; \
	ldxa		[REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
	USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, 800f) \
	sllx		VADDR, 64 - PMD_SHIFT, REG2; \
	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
	andn		REG2, 0x7, REG2; \
	add		REG1, REG2, REG1; \
	ldxa		[REG1] ASI_PHYS_USE_EC, REG1; \
	brgez,pn	REG1, FAIL_LABEL; \
	 nop; \
800:

/* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0.
 * If no entry is found, FAIL_LABEL will be branched to.  On success
 * the resulting PTE value will be left in REG1.  VADDR is preserved
 * by this routine.
 */
#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
	sethi		%hi(prom_trans), REG1; \
	or		REG1, %lo(prom_trans), REG1; \
97:	ldx		[REG1 + 0x00], REG2; \
	brz,pn		REG2, FAIL_LABEL; \
	 nop; \
	ldx		[REG1 + 0x08], REG3; \
	add		REG2, REG3, REG3; \
	cmp		REG2, VADDR; \
	bgu,pt		%xcc, 98f; \
	 cmp		VADDR, REG3; \
	bgeu,pt		%xcc, 98f; \
	 ldx		[REG1 + 0x10], REG3; \
	sub		VADDR, REG2, REG2; \
	ba,pt		%xcc, 99f; \
	 add		REG3, REG2, REG1; \
98:	ba,pt		%xcc, 97b; \
	 add		REG1, (3 * 8), REG1; \
99:

/* We use a 32K TSB for the whole kernel, this allows to
	 * handle about 16MB of modules and vmalloc mappings without
	 * incurring many hash conflicts.
	 */
#define KERNEL_TSB_SIZE_BYTES	(32 * 1024)
#define KERNEL_TSB_NENTRIES	\
	(KERNEL_TSB_SIZE_BYTES / 16)
#define KERNEL_TSB4M_NENTRIES	4096

/* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL
	 * on TSB hit.  REG1, REG2, REG3, and REG4 are used as temporaries
	 * and the found TTE will be left in REG1.  REG3 and REG4 must
	 * be an even/odd pair of registers.
	 *
	 * VADDR and TAG will be preserved and not clobbered by this macro.
	 */
#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
661:	sethi		%uhi(swapper_tsb), REG1; \
	sethi		%hi(swapper_tsb), REG2; \
	or		REG1, %ulo(swapper_tsb), REG1; \
	or		REG2, %lo(swapper_tsb), REG2; \
	.section	.swapper_tsb_phys_patch, "ax"; \
	.word		661b; \
	.previous; \
	sllx		REG1, 32, REG1; \
	or		REG1, REG2, REG1; \
	srlx		VADDR, PAGE_SHIFT, REG2; \
	and		REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
	sllx		REG2, 4, REG2; \
	add		REG1, REG2, REG2; \
	TSB_LOAD_QUAD(REG2, REG3); \
	cmp		REG3, TAG; \
	be,a,pt		%xcc, OK_LABEL; \
	 mov		REG4, REG1;

#ifndef CONFIG_DEBUG_PAGEALLOC
	/* This version uses a trick, the TAG is already (VADDR >> 22) so
	 * we can make use of that for the index computation.
	 */
#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
661:	sethi		%uhi(swapper_4m_tsb), REG1; \
	sethi		%hi(swapper_4m_tsb), REG2; \
	or		REG1, %ulo(swapper_4m_tsb), REG1; \
	or		REG2, %lo(swapper_4m_tsb), REG2; \
	.section	.swapper_4m_tsb_phys_patch, "ax"; \
	.word		661b; \
	.previous; \
	sllx		REG1, 32, REG1; \
	or		REG1, REG2, REG1; \
	and		TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
	sllx		REG2, 4, REG2; \
	add		REG1, REG2, REG2; \
	TSB_LOAD_QUAD(REG2, REG3); \
	cmp		REG3, TAG; \
	be,a,pt		%xcc, OK_LABEL; \
	 mov		REG4, REG1;
#endif

#endif /* !(_SPARC64_TSB_H) */