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06/12/2025 06:19:49 PM
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amdgpu_drm.h
38.36 KB
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armada_drm.h
1.18 KB
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drm.h
44.6 KB
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drm_fourcc.h
67.83 KB
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drm_mode.h
40.23 KB
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drm_sarea.h
2.72 KB
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etnaviv_drm.h
11.71 KB
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exynos_drm.h
10.87 KB
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habanalabs_accel.h
79.61 KB
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i915_drm.h
126.65 KB
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ivpu_accel.h
9.25 KB
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lima_drm.h
4.93 KB
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msm_drm.h
16.1 KB
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nouveau_drm.h
14.17 KB
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omap_drm.h
3.93 KB
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panfrost_drm.h
8.25 KB
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pvr_drm.h
39.22 KB
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qaic_accel.h
12.39 KB
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qxl_drm.h
4.03 KB
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radeon_drm.h
37.34 KB
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tegra_drm.h
21.13 KB
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v3d_drm.h
21.56 KB
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vc4_drm.h
14.12 KB
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vgem_drm.h
1.92 KB
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virtgpu_drm.h
7.66 KB
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vmwgfx_drm.h
36.6 KB
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xe_drm.h
44.56 KB
04/15/2025 05:24:36 PM
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Editing: drm_sarea.h
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/** * \file drm_sarea.h * \brief SAREA definitions * * \author Michel DΓ€nzer <michel@daenzer.net> */ /* * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _DRM_SAREA_H_ #define _DRM_SAREA_H_ #include "drm.h" #if defined(__cplusplus) extern "C" { #endif /* SAREA area needs to be at least a page */ #if defined(__alpha__) #define SAREA_MAX 0x2000U #elif defined(__mips__) #define SAREA_MAX 0x4000U #elif defined(__ia64__) #define SAREA_MAX 0x10000U /* 64kB */ #else /* Intel 830M driver needs at least 8k SAREA */ #define SAREA_MAX 0x2000U #endif /** Maximum number of drawables in the SAREA */ #define SAREA_MAX_DRAWABLES 256 #define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000 /** SAREA drawable */ struct drm_sarea_drawable { unsigned int stamp; unsigned int flags; }; /** SAREA frame */ struct drm_sarea_frame { unsigned int x; unsigned int y; unsigned int width; unsigned int height; unsigned int fullscreen; }; /** SAREA */ struct drm_sarea { /** first thing is always the DRM locking structure */ struct drm_hw_lock lock; /** \todo Use readers/writer lock for drm_sarea::drawable_lock */ struct drm_hw_lock drawable_lock; struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */ struct drm_sarea_frame frame; /**< frame */ drm_context_t dummy_context; }; typedef struct drm_sarea_drawable drm_sarea_drawable_t; typedef struct drm_sarea_frame drm_sarea_frame_t; typedef struct drm_sarea drm_sarea_t; #if defined(__cplusplus) } #endif #endif /* _DRM_SAREA_H_ */