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linux-headers-4.15.0-213
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include
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asm
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..
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05/09/2024 07:14:13 AM
rwxr-xr-x
📄
Kbuild
294 bytes
01/28/2018 09:20:33 PM
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a.out-core.h
1.89 KB
01/28/2018 09:20:33 PM
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acenv.h
1.56 KB
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acpi.h
4.76 KB
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agp.h
1.04 KB
01/28/2018 09:20:33 PM
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alternative-asm.h
2.43 KB
01/28/2018 09:20:33 PM
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alternative.h
8.28 KB
06/16/2023 05:32:39 PM
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amd_nb.h
2.98 KB
01/28/2018 09:20:33 PM
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apb_timer.h
1.43 KB
01/28/2018 09:20:33 PM
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apic.h
14.53 KB
06/16/2023 05:32:39 PM
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apic_flat_64.h
151 bytes
01/28/2018 09:20:33 PM
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apicdef.h
11.26 KB
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apm.h
1.8 KB
06/16/2023 05:32:39 PM
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arch_hweight.h
1.28 KB
01/28/2018 09:20:33 PM
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archrandom.h
3.03 KB
06/16/2023 05:32:39 PM
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asm-offsets.h
35 bytes
01/28/2018 09:20:33 PM
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asm-prototypes.h
946 bytes
01/28/2018 09:20:33 PM
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asm.h
4.97 KB
06/16/2023 05:32:39 PM
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atomic.h
6.02 KB
06/16/2023 05:32:39 PM
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atomic64_32.h
8.71 KB
01/28/2018 09:20:33 PM
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atomic64_64.h
6.31 KB
06/16/2023 05:32:39 PM
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barrier.h
3.6 KB
06/16/2023 05:32:39 PM
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bios_ebda.h
914 bytes
01/28/2018 09:20:33 PM
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bitops.h
13.78 KB
06/16/2023 05:32:39 PM
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boot.h
1.53 KB
01/28/2018 09:20:33 PM
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bootparam_utils.h
2.86 KB
06/16/2023 05:32:39 PM
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bug.h
2.07 KB
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bugs.h
493 bytes
01/28/2018 09:20:33 PM
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cache.h
641 bytes
01/28/2018 09:20:33 PM
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cacheflush.h
306 bytes
01/28/2018 09:20:33 PM
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cacheinfo.h
209 bytes
06/16/2023 05:32:39 PM
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calgary.h
2.31 KB
01/28/2018 09:20:33 PM
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ce4100.h
121 bytes
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checksum.h
133 bytes
01/28/2018 09:20:33 PM
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checksum_32.h
4.86 KB
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checksum_64.h
5.41 KB
01/28/2018 09:20:33 PM
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clocksource.h
488 bytes
01/28/2018 09:20:33 PM
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cmdline.h
302 bytes
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cmpxchg.h
7.68 KB
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cmpxchg_32.h
3.15 KB
01/28/2018 09:20:33 PM
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cmpxchg_64.h
543 bytes
01/28/2018 09:20:33 PM
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compat.h
7.37 KB
06/16/2023 05:32:39 PM
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cpu.h
975 bytes
01/28/2018 09:20:33 PM
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cpu_device_id.h
7.39 KB
06/16/2023 05:32:39 PM
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cpu_entry_area.h
2.27 KB
01/28/2018 09:20:33 PM
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cpufeature.h
7.75 KB
06/16/2023 05:32:39 PM
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cpufeatures.h
25.59 KB
06/16/2023 05:32:39 PM
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cpumask.h
408 bytes
01/28/2018 09:20:33 PM
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crash.h
320 bytes
06/16/2023 05:32:39 PM
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crypto
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05/09/2024 07:14:16 AM
rwxr-xr-x
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current.h
443 bytes
01/28/2018 09:20:33 PM
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debugreg.h
2.67 KB
01/28/2018 09:20:33 PM
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delay.h
208 bytes
01/28/2018 09:20:33 PM
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desc.h
11.42 KB
01/28/2018 09:20:33 PM
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desc_defs.h
3.16 KB
01/28/2018 09:20:33 PM
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device.h
568 bytes
01/28/2018 09:20:33 PM
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disabled-features.h
2.31 KB
06/16/2023 05:32:39 PM
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div64.h
1.79 KB
01/28/2018 09:20:33 PM
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dma-mapping.h
2.4 KB
01/28/2018 09:20:33 PM
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dma.h
9.58 KB
06/16/2023 05:32:39 PM
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dmi.h
556 bytes
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dwarf2.h
2.43 KB
01/28/2018 09:20:33 PM
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e820
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05/09/2024 07:14:16 AM
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edac.h
474 bytes
01/28/2018 09:20:33 PM
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efi.h
6.9 KB
06/16/2023 05:32:39 PM
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elf.h
10.82 KB
01/28/2018 09:20:33 PM
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emergency-restart.h
202 bytes
01/28/2018 09:20:33 PM
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entry_arch.h
1.88 KB
01/28/2018 09:20:33 PM
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espfix.h
426 bytes
01/28/2018 09:20:33 PM
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exec.h
37 bytes
01/28/2018 09:20:33 PM
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export.h
120 bytes
01/28/2018 09:20:33 PM
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extable.h
1.27 KB
01/28/2018 09:20:33 PM
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fb.h
540 bytes
01/28/2018 09:20:33 PM
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fixmap.h
6.04 KB
06/16/2023 05:32:39 PM
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floppy.h
6.59 KB
01/28/2018 09:20:33 PM
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📁
fpu
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05/09/2024 07:14:16 AM
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frame.h
815 bytes
01/28/2018 09:20:33 PM
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ftrace.h
1.8 KB
01/28/2018 09:20:33 PM
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futex.h
2.2 KB
01/28/2018 09:20:33 PM
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gart.h
2.64 KB
01/28/2018 09:20:33 PM
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genapic.h
22 bytes
01/28/2018 09:20:33 PM
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geode.h
842 bytes
01/28/2018 09:20:33 PM
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hardirq.h
2.3 KB
06/16/2023 05:32:39 PM
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highmem.h
2.6 KB
01/28/2018 09:20:33 PM
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hpet.h
3.38 KB
01/28/2018 09:20:33 PM
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hugetlb.h
2.15 KB
01/28/2018 09:20:33 PM
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hw_breakpoint.h
1.96 KB
01/28/2018 09:20:33 PM
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hw_irq.h
3.85 KB
06/16/2023 05:32:39 PM
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hypervisor.h
1.84 KB
01/28/2018 09:20:33 PM
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i8259.h
1.93 KB
06/16/2023 05:32:39 PM
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ia32.h
1.46 KB
01/28/2018 09:20:33 PM
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ia32_unistd.h
313 bytes
01/28/2018 09:20:33 PM
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imr.h
1.81 KB
01/28/2018 09:20:33 PM
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inat.h
6.58 KB
01/28/2018 09:20:33 PM
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📄
inat_types.h
1013 bytes
01/28/2018 09:20:33 PM
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📄
init.h
632 bytes
01/28/2018 09:20:33 PM
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insn-eval.h
837 bytes
01/28/2018 09:20:33 PM
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insn.h
7.46 KB
06/16/2023 05:32:39 PM
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inst.h
5.07 KB
01/28/2018 09:20:33 PM
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📄
intel-family.h
3.47 KB
06/16/2023 05:32:39 PM
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intel-mid.h
4.91 KB
01/28/2018 09:20:33 PM
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intel_ds.h
793 bytes
01/28/2018 09:20:33 PM
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📄
intel_mid_vrtc.h
326 bytes
01/28/2018 09:20:33 PM
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intel_pmc_ipc.h
2.08 KB
01/28/2018 09:20:33 PM
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intel_pt.h
292 bytes
01/28/2018 09:20:33 PM
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📄
intel_punit_ipc.h
4.56 KB
01/28/2018 09:20:33 PM
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📄
intel_rdt_sched.h
2.59 KB
01/28/2018 09:20:33 PM
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intel_scu_ipc.h
2.3 KB
01/28/2018 09:20:33 PM
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📄
intel_telemetry.h
3.96 KB
01/28/2018 09:20:33 PM
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invpcid.h
1.57 KB
01/28/2018 09:20:33 PM
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📄
io.h
12.21 KB
01/28/2018 09:20:33 PM
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io_apic.h
5.63 KB
01/28/2018 09:20:33 PM
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iomap.h
1.22 KB
01/28/2018 09:20:33 PM
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iommu.h
392 bytes
01/28/2018 09:20:33 PM
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iommu_table.h
3.82 KB
01/28/2018 09:20:33 PM
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iosf_mbi.h
5.74 KB
01/28/2018 09:20:33 PM
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ipi.h
2.84 KB
01/28/2018 09:20:33 PM
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irq.h
1.12 KB
01/28/2018 09:20:33 PM
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irq_regs.h
679 bytes
01/28/2018 09:20:33 PM
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irq_remapping.h
2.96 KB
06/16/2023 05:32:39 PM
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irq_vectors.h
4.12 KB
01/28/2018 09:20:33 PM
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irq_work.h
397 bytes
01/28/2018 09:20:33 PM
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irqdomain.h
1.61 KB
01/28/2018 09:20:33 PM
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irqflags.h
4.38 KB
06/16/2023 05:32:39 PM
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ist.h
735 bytes
01/28/2018 09:20:33 PM
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jump_label.h
2.44 KB
01/28/2018 09:20:33 PM
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kasan.h
966 bytes
01/28/2018 09:20:33 PM
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kaslr.h
424 bytes
01/28/2018 09:20:33 PM
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kbdleds.h
454 bytes
01/28/2018 09:20:33 PM
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kdebug.h
752 bytes
01/28/2018 09:20:33 PM
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kexec-bzimage64.h
189 bytes
01/28/2018 09:20:33 PM
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kexec.h
6.69 KB
06/16/2023 05:32:39 PM
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kgdb.h
2.09 KB
01/28/2018 09:20:33 PM
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kmap_types.h
289 bytes
01/28/2018 09:20:33 PM
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kprobes.h
3.82 KB
01/28/2018 09:20:33 PM
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kvm_emulate.h
15.23 KB
06/16/2023 05:32:39 PM
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kvm_guest.h
172 bytes
01/28/2018 09:20:33 PM
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kvm_host.h
42.72 KB
06/16/2023 05:32:39 PM
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kvm_page_track.h
2.48 KB
01/28/2018 09:20:33 PM
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kvm_para.h
3 KB
01/28/2018 09:20:33 PM
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kvmclock.h
170 bytes
01/28/2018 09:20:33 PM
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linkage.h
581 bytes
01/28/2018 09:20:33 PM
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livepatch.h
1.12 KB
01/28/2018 09:20:33 PM
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local.h
3.83 KB
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local64.h
33 bytes
01/28/2018 09:20:33 PM
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mach_timer.h
1.55 KB
01/28/2018 09:20:33 PM
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mach_traps.h
1013 bytes
01/28/2018 09:20:33 PM
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math_emu.h
395 bytes
01/28/2018 09:20:33 PM
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mc146818rtc.h
2.76 KB
01/28/2018 09:20:33 PM
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mce.h
12.54 KB
06/16/2023 05:32:39 PM
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mem_encrypt.h
2.83 KB
01/28/2018 09:20:33 PM
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microcode.h
4.14 KB
06/16/2023 05:32:39 PM
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microcode_amd.h
1.41 KB
06/16/2023 05:32:39 PM
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microcode_intel.h
2.46 KB
01/28/2018 09:20:33 PM
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misc.h
143 bytes
01/28/2018 09:20:33 PM
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mmconfig.h
374 bytes
01/28/2018 09:20:33 PM
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mmu.h
1.57 KB
01/28/2018 09:20:33 PM
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mmu_context.h
10.27 KB
06/16/2023 05:32:39 PM
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mmx.h
337 bytes
01/28/2018 09:20:33 PM
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mmzone.h
129 bytes
01/28/2018 09:20:33 PM
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mmzone_32.h
1.16 KB
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mmzone_64.h
430 bytes
01/28/2018 09:20:33 PM
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module.h
2.05 KB
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mpspec.h
3.93 KB
01/28/2018 09:20:33 PM
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mpspec_def.h
3.93 KB
01/28/2018 09:20:33 PM
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mpx.h
2.97 KB
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mshyperv.h
10.69 KB
01/28/2018 09:20:33 PM
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msi.h
392 bytes
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msidef.h
1.77 KB
01/28/2018 09:20:33 PM
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msr-index.h
30.92 KB
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msr-trace.h
1.35 KB
01/28/2018 09:20:33 PM
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msr.h
10.85 KB
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mtrr.h
4.62 KB
01/28/2018 09:20:33 PM
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mwait.h
3.74 KB
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nmi.h
1.39 KB
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nops.h
4.31 KB
01/28/2018 09:20:33 PM
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nospec-branch.h
11.49 KB
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numa.h
2.18 KB
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numa_32.h
256 bytes
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numachip
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olpc.h
3.16 KB
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olpc_ofw.h
1.1 KB
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orc_lookup.h
1.63 KB
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orc_types.h
3.47 KB
01/28/2018 09:20:33 PM
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page.h
2.18 KB
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page_32.h
1.01 KB
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page_32_types.h
1.7 KB
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page_64.h
1.42 KB
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page_64_types.h
2.34 KB
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page_types.h
2.29 KB
01/28/2018 09:20:33 PM
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paravirt.h
23.31 KB
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paravirt_types.h
22.15 KB
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parport.h
314 bytes
01/28/2018 09:20:33 PM
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pat.h
768 bytes
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pci-direct.h
995 bytes
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pci-functions.h
654 bytes
01/28/2018 09:20:33 PM
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pci.h
3.51 KB
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pci_64.h
684 bytes
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pci_x86.h
5.71 KB
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percpu.h
18.97 KB
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perf_event.h
8.82 KB
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perf_event_p4.h
26.1 KB
01/28/2018 09:20:33 PM
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pgalloc.h
5.57 KB
01/28/2018 09:20:33 PM
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pgtable-2level.h
2.75 KB
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pgtable-2level_types.h
867 bytes
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pgtable-3level.h
10.24 KB
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pgtable-3level_types.h
1.06 KB
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pgtable-invert.h
1.07 KB
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pgtable.h
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Editing: xor_32.h
Close
#ifndef _ASM_X86_XOR_32_H #define _ASM_X86_XOR_32_H /* * Optimized RAID-5 checksumming functions for MMX. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2, or (at your option) * any later version. * * You should have received a copy of the GNU General Public License * (for example /usr/src/linux/COPYING); if not, write to the Free * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* * High-speed RAID5 checksumming functions utilizing MMX instructions. * Copyright (C) 1998 Ingo Molnar. */ #define LD(x, y) " movq 8*("#x")(%1), %%mm"#y" ;\n" #define ST(x, y) " movq %%mm"#y", 8*("#x")(%1) ;\n" #define XO1(x, y) " pxor 8*("#x")(%2), %%mm"#y" ;\n" #define XO2(x, y) " pxor 8*("#x")(%3), %%mm"#y" ;\n" #define XO3(x, y) " pxor 8*("#x")(%4), %%mm"#y" ;\n" #define XO4(x, y) " pxor 8*("#x")(%5), %%mm"#y" ;\n" #include <asm/fpu/api.h> static void xor_pII_mmx_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) { unsigned long lines = bytes >> 7; kernel_fpu_begin(); asm volatile( #undef BLOCK #define BLOCK(i) \ LD(i, 0) \ LD(i + 1, 1) \ LD(i + 2, 2) \ LD(i + 3, 3) \ XO1(i, 0) \ ST(i, 0) \ XO1(i+1, 1) \ ST(i+1, 1) \ XO1(i + 2, 2) \ ST(i + 2, 2) \ XO1(i + 3, 3) \ ST(i + 3, 3) " .align 32 ;\n" " 1: ;\n" BLOCK(0) BLOCK(4) BLOCK(8) BLOCK(12) " addl $128, %1 ;\n" " addl $128, %2 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2) : : "memory"); kernel_fpu_end(); } static void xor_pII_mmx_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, unsigned long *p3) { unsigned long lines = bytes >> 7; kernel_fpu_begin(); asm volatile( #undef BLOCK #define BLOCK(i) \ LD(i, 0) \ LD(i + 1, 1) \ LD(i + 2, 2) \ LD(i + 3, 3) \ XO1(i, 0) \ XO1(i + 1, 1) \ XO1(i + 2, 2) \ XO1(i + 3, 3) \ XO2(i, 0) \ ST(i, 0) \ XO2(i + 1, 1) \ ST(i + 1, 1) \ XO2(i + 2, 2) \ ST(i + 2, 2) \ XO2(i + 3, 3) \ ST(i + 3, 3) " .align 32 ;\n" " 1: ;\n" BLOCK(0) BLOCK(4) BLOCK(8) BLOCK(12) " addl $128, %1 ;\n" " addl $128, %2 ;\n" " addl $128, %3 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2), "+r" (p3) : : "memory"); kernel_fpu_end(); } static void xor_pII_mmx_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, unsigned long *p3, unsigned long *p4) { unsigned long lines = bytes >> 7; kernel_fpu_begin(); asm volatile( #undef BLOCK #define BLOCK(i) \ LD(i, 0) \ LD(i + 1, 1) \ LD(i + 2, 2) \ LD(i + 3, 3) \ XO1(i, 0) \ XO1(i + 1, 1) \ XO1(i + 2, 2) \ XO1(i + 3, 3) \ XO2(i, 0) \ XO2(i + 1, 1) \ XO2(i + 2, 2) \ XO2(i + 3, 3) \ XO3(i, 0) \ ST(i, 0) \ XO3(i + 1, 1) \ ST(i + 1, 1) \ XO3(i + 2, 2) \ ST(i + 2, 2) \ XO3(i + 3, 3) \ ST(i + 3, 3) " .align 32 ;\n" " 1: ;\n" BLOCK(0) BLOCK(4) BLOCK(8) BLOCK(12) " addl $128, %1 ;\n" " addl $128, %2 ;\n" " addl $128, %3 ;\n" " addl $128, %4 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4) : : "memory"); kernel_fpu_end(); } static void xor_pII_mmx_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, unsigned long *p3, unsigned long *p4, unsigned long *p5) { unsigned long lines = bytes >> 7; kernel_fpu_begin(); /* Make sure GCC forgets anything it knows about p4 or p5, such that it won't pass to the asm volatile below a register that is shared with any other variable. That's because we modify p4 and p5 there, but we can't mark them as read/write, otherwise we'd overflow the 10-asm-operands limit of GCC < 3.1. */ asm("" : "+r" (p4), "+r" (p5)); asm volatile( #undef BLOCK #define BLOCK(i) \ LD(i, 0) \ LD(i + 1, 1) \ LD(i + 2, 2) \ LD(i + 3, 3) \ XO1(i, 0) \ XO1(i + 1, 1) \ XO1(i + 2, 2) \ XO1(i + 3, 3) \ XO2(i, 0) \ XO2(i + 1, 1) \ XO2(i + 2, 2) \ XO2(i + 3, 3) \ XO3(i, 0) \ XO3(i + 1, 1) \ XO3(i + 2, 2) \ XO3(i + 3, 3) \ XO4(i, 0) \ ST(i, 0) \ XO4(i + 1, 1) \ ST(i + 1, 1) \ XO4(i + 2, 2) \ ST(i + 2, 2) \ XO4(i + 3, 3) \ ST(i + 3, 3) " .align 32 ;\n" " 1: ;\n" BLOCK(0) BLOCK(4) BLOCK(8) BLOCK(12) " addl $128, %1 ;\n" " addl $128, %2 ;\n" " addl $128, %3 ;\n" " addl $128, %4 ;\n" " addl $128, %5 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2), "+r" (p3) : "r" (p4), "r" (p5) : "memory"); /* p4 and p5 were modified, and now the variables are dead. Clobber them just to be sure nobody does something stupid like assuming they have some legal value. */ asm("" : "=r" (p4), "=r" (p5)); kernel_fpu_end(); } #undef LD #undef XO1 #undef XO2 #undef XO3 #undef XO4 #undef ST #undef BLOCK static void xor_p5_mmx_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) { unsigned long lines = bytes >> 6; kernel_fpu_begin(); asm volatile( " .align 32 ;\n" " 1: ;\n" " movq (%1), %%mm0 ;\n" " movq 8(%1), %%mm1 ;\n" " pxor (%2), %%mm0 ;\n" " movq 16(%1), %%mm2 ;\n" " movq %%mm0, (%1) ;\n" " pxor 8(%2), %%mm1 ;\n" " movq 24(%1), %%mm3 ;\n" " movq %%mm1, 8(%1) ;\n" " pxor 16(%2), %%mm2 ;\n" " movq 32(%1), %%mm4 ;\n" " movq %%mm2, 16(%1) ;\n" " pxor 24(%2), %%mm3 ;\n" " movq 40(%1), %%mm5 ;\n" " movq %%mm3, 24(%1) ;\n" " pxor 32(%2), %%mm4 ;\n" " movq 48(%1), %%mm6 ;\n" " movq %%mm4, 32(%1) ;\n" " pxor 40(%2), %%mm5 ;\n" " movq 56(%1), %%mm7 ;\n" " movq %%mm5, 40(%1) ;\n" " pxor 48(%2), %%mm6 ;\n" " pxor 56(%2), %%mm7 ;\n" " movq %%mm6, 48(%1) ;\n" " movq %%mm7, 56(%1) ;\n" " addl $64, %1 ;\n" " addl $64, %2 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2) : : "memory"); kernel_fpu_end(); } static void xor_p5_mmx_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, unsigned long *p3) { unsigned long lines = bytes >> 6; kernel_fpu_begin(); asm volatile( " .align 32,0x90 ;\n" " 1: ;\n" " movq (%1), %%mm0 ;\n" " movq 8(%1), %%mm1 ;\n" " pxor (%2), %%mm0 ;\n" " movq 16(%1), %%mm2 ;\n" " pxor 8(%2), %%mm1 ;\n" " pxor (%3), %%mm0 ;\n" " pxor 16(%2), %%mm2 ;\n" " movq %%mm0, (%1) ;\n" " pxor 8(%3), %%mm1 ;\n" " pxor 16(%3), %%mm2 ;\n" " movq 24(%1), %%mm3 ;\n" " movq %%mm1, 8(%1) ;\n" " movq 32(%1), %%mm4 ;\n" " movq 40(%1), %%mm5 ;\n" " pxor 24(%2), %%mm3 ;\n" " movq %%mm2, 16(%1) ;\n" " pxor 32(%2), %%mm4 ;\n" " pxor 24(%3), %%mm3 ;\n" " pxor 40(%2), %%mm5 ;\n" " movq %%mm3, 24(%1) ;\n" " pxor 32(%3), %%mm4 ;\n" " pxor 40(%3), %%mm5 ;\n" " movq 48(%1), %%mm6 ;\n" " movq %%mm4, 32(%1) ;\n" " movq 56(%1), %%mm7 ;\n" " pxor 48(%2), %%mm6 ;\n" " movq %%mm5, 40(%1) ;\n" " pxor 56(%2), %%mm7 ;\n" " pxor 48(%3), %%mm6 ;\n" " pxor 56(%3), %%mm7 ;\n" " movq %%mm6, 48(%1) ;\n" " movq %%mm7, 56(%1) ;\n" " addl $64, %1 ;\n" " addl $64, %2 ;\n" " addl $64, %3 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2), "+r" (p3) : : "memory" ); kernel_fpu_end(); } static void xor_p5_mmx_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, unsigned long *p3, unsigned long *p4) { unsigned long lines = bytes >> 6; kernel_fpu_begin(); asm volatile( " .align 32,0x90 ;\n" " 1: ;\n" " movq (%1), %%mm0 ;\n" " movq 8(%1), %%mm1 ;\n" " pxor (%2), %%mm0 ;\n" " movq 16(%1), %%mm2 ;\n" " pxor 8(%2), %%mm1 ;\n" " pxor (%3), %%mm0 ;\n" " pxor 16(%2), %%mm2 ;\n" " pxor 8(%3), %%mm1 ;\n" " pxor (%4), %%mm0 ;\n" " movq 24(%1), %%mm3 ;\n" " pxor 16(%3), %%mm2 ;\n" " pxor 8(%4), %%mm1 ;\n" " movq %%mm0, (%1) ;\n" " movq 32(%1), %%mm4 ;\n" " pxor 24(%2), %%mm3 ;\n" " pxor 16(%4), %%mm2 ;\n" " movq %%mm1, 8(%1) ;\n" " movq 40(%1), %%mm5 ;\n" " pxor 32(%2), %%mm4 ;\n" " pxor 24(%3), %%mm3 ;\n" " movq %%mm2, 16(%1) ;\n" " pxor 40(%2), %%mm5 ;\n" " pxor 32(%3), %%mm4 ;\n" " pxor 24(%4), %%mm3 ;\n" " movq %%mm3, 24(%1) ;\n" " movq 56(%1), %%mm7 ;\n" " movq 48(%1), %%mm6 ;\n" " pxor 40(%3), %%mm5 ;\n" " pxor 32(%4), %%mm4 ;\n" " pxor 48(%2), %%mm6 ;\n" " movq %%mm4, 32(%1) ;\n" " pxor 56(%2), %%mm7 ;\n" " pxor 40(%4), %%mm5 ;\n" " pxor 48(%3), %%mm6 ;\n" " pxor 56(%3), %%mm7 ;\n" " movq %%mm5, 40(%1) ;\n" " pxor 48(%4), %%mm6 ;\n" " pxor 56(%4), %%mm7 ;\n" " movq %%mm6, 48(%1) ;\n" " movq %%mm7, 56(%1) ;\n" " addl $64, %1 ;\n" " addl $64, %2 ;\n" " addl $64, %3 ;\n" " addl $64, %4 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4) : : "memory"); kernel_fpu_end(); } static void xor_p5_mmx_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, unsigned long *p3, unsigned long *p4, unsigned long *p5) { unsigned long lines = bytes >> 6; kernel_fpu_begin(); /* Make sure GCC forgets anything it knows about p4 or p5, such that it won't pass to the asm volatile below a register that is shared with any other variable. That's because we modify p4 and p5 there, but we can't mark them as read/write, otherwise we'd overflow the 10-asm-operands limit of GCC < 3.1. */ asm("" : "+r" (p4), "+r" (p5)); asm volatile( " .align 32,0x90 ;\n" " 1: ;\n" " movq (%1), %%mm0 ;\n" " movq 8(%1), %%mm1 ;\n" " pxor (%2), %%mm0 ;\n" " pxor 8(%2), %%mm1 ;\n" " movq 16(%1), %%mm2 ;\n" " pxor (%3), %%mm0 ;\n" " pxor 8(%3), %%mm1 ;\n" " pxor 16(%2), %%mm2 ;\n" " pxor (%4), %%mm0 ;\n" " pxor 8(%4), %%mm1 ;\n" " pxor 16(%3), %%mm2 ;\n" " movq 24(%1), %%mm3 ;\n" " pxor (%5), %%mm0 ;\n" " pxor 8(%5), %%mm1 ;\n" " movq %%mm0, (%1) ;\n" " pxor 16(%4), %%mm2 ;\n" " pxor 24(%2), %%mm3 ;\n" " movq %%mm1, 8(%1) ;\n" " pxor 16(%5), %%mm2 ;\n" " pxor 24(%3), %%mm3 ;\n" " movq 32(%1), %%mm4 ;\n" " movq %%mm2, 16(%1) ;\n" " pxor 24(%4), %%mm3 ;\n" " pxor 32(%2), %%mm4 ;\n" " movq 40(%1), %%mm5 ;\n" " pxor 24(%5), %%mm3 ;\n" " pxor 32(%3), %%mm4 ;\n" " pxor 40(%2), %%mm5 ;\n" " movq %%mm3, 24(%1) ;\n" " pxor 32(%4), %%mm4 ;\n" " pxor 40(%3), %%mm5 ;\n" " movq 48(%1), %%mm6 ;\n" " movq 56(%1), %%mm7 ;\n" " pxor 32(%5), %%mm4 ;\n" " pxor 40(%4), %%mm5 ;\n" " pxor 48(%2), %%mm6 ;\n" " pxor 56(%2), %%mm7 ;\n" " movq %%mm4, 32(%1) ;\n" " pxor 48(%3), %%mm6 ;\n" " pxor 56(%3), %%mm7 ;\n" " pxor 40(%5), %%mm5 ;\n" " pxor 48(%4), %%mm6 ;\n" " pxor 56(%4), %%mm7 ;\n" " movq %%mm5, 40(%1) ;\n" " pxor 48(%5), %%mm6 ;\n" " pxor 56(%5), %%mm7 ;\n" " movq %%mm6, 48(%1) ;\n" " movq %%mm7, 56(%1) ;\n" " addl $64, %1 ;\n" " addl $64, %2 ;\n" " addl $64, %3 ;\n" " addl $64, %4 ;\n" " addl $64, %5 ;\n" " decl %0 ;\n" " jnz 1b ;\n" : "+r" (lines), "+r" (p1), "+r" (p2), "+r" (p3) : "r" (p4), "r" (p5) : "memory"); /* p4 and p5 were modified, and now the variables are dead. Clobber them just to be sure nobody does something stupid like assuming they have some legal value. */ asm("" : "=r" (p4), "=r" (p5)); kernel_fpu_end(); } static struct xor_block_template xor_block_pII_mmx = { .name = "pII_mmx", .do_2 = xor_pII_mmx_2, .do_3 = xor_pII_mmx_3, .do_4 = xor_pII_mmx_4, .do_5 = xor_pII_mmx_5, }; static struct xor_block_template xor_block_p5_mmx = { .name = "p5_mmx", .do_2 = xor_p5_mmx_2, .do_3 = xor_p5_mmx_3, .do_4 = xor_p5_mmx_4, .do_5 = xor_p5_mmx_5, }; static struct xor_block_template xor_block_pIII_sse = { .name = "pIII_sse", .do_2 = xor_sse_2, .do_3 = xor_sse_3, .do_4 = xor_sse_4, .do_5 = xor_sse_5, }; /* Also try the AVX routines */ #include <asm/xor_avx.h> /* Also try the generic routines. */ #include <asm-generic/xor.h> /* We force the use of the SSE xor block because it can write around L2. We may also be able to load into the L1 only depending on how the cpu deals with a load to a line that is being prefetched. */ #undef XOR_TRY_TEMPLATES #define XOR_TRY_TEMPLATES \ do { \ AVX_XOR_SPEED; \ if (boot_cpu_has(X86_FEATURE_XMM)) { \ xor_speed(&xor_block_pIII_sse); \ xor_speed(&xor_block_sse_pf64); \ } else if (boot_cpu_has(X86_FEATURE_MMX)) { \ xor_speed(&xor_block_pII_mmx); \ xor_speed(&xor_block_p5_mmx); \ } else { \ xor_speed(&xor_block_8regs); \ xor_speed(&xor_block_8regs_p); \ xor_speed(&xor_block_32regs); \ xor_speed(&xor_block_32regs_p); \ } \ } while (0) #endif /* _ASM_X86_XOR_32_H */