OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	05/09/2024 07:14:13 AM	rwxr-xr-x
📄 8xx_immap.h	13.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 Kbuild	248 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 accounting.h	1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 agp.h	525 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 archrandom.h	1016 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 asm-compat.h	2.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-prototypes.h	4.78 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 async_tx.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	13.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 backlight.h	1.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	3.57 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 bitops.h	7.8 KB	06/16/2023 05:32:39 PM	rw-r--r--
📁 book3s	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 bootx.h	1.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 btext.h	926 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	3.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	486 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	2.47 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cacheflush.h	3.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cell-pmu.h	4.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cell-regs.h	9.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	5.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	12.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 code-patching-asm.h	397 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 code-patching.h	5.01 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 compat.h	6.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 context_tracking.h	245 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 copro.h	769 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpm.h	5.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpm1.h	21.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpm2.h	48.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu_has_feature.h	1.31 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cpufeature.h	1.18 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpuidle.h	3.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cputable.h	22.56 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cputhreads.h	2.92 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 cputime.h	1.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	835 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dbdma.h	3.72 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dbell.h	2.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr-generic.h	1.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr-mmio.h	1.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr-native.h	4.42 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 dcr-regs.h	5.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dcr.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug.h	1.97 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 debugfs.h	489 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	3.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 device.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 disassemble.h	2.73 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	4.12 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	10.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 dt_cpu_ftrs.h	816 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 edac.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeh.h	14.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 eeh_event.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ehv_pic.h	963 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	6.29 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 emergency-restart.h	43 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 emulated_ops.h	2.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 epapr_hcalls.h	16.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exception-64e.h	7.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 exception-64s.h	22.72 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 exec.h	246 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	904 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 fadump.h	6.1 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 fb.h	483 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 feature-fixups.h	8.76 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 firmware.h	4.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 floppy.h	4.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fs_pd.h	1.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_85xx_cache_sram.h	1.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_gtm.h	1.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_hcalls.h	17.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_lbc.h	10.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_pamu_stash.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fsl_pm.h	1.36 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ftrace.h	2.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 grackle.h	331 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	1.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 head-64.h	13.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 heathrow.h	2.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 highmem.h	2.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hmi.h	1.49 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hugetlb.h	4.73 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hvcall.h	15.35 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hvconsole.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hvcserver.h	2.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hvsi.h	2.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_breakpoint.h	3.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	5.24 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 hydra.h	2.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 i8259.h	361 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ibmebus.h	2.15 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 icswx.h	4.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ide.h	586 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ima.h	772 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 imc-pmu.h	2.87 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 immap_cpm2.h	10.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-defs.h	3.09 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io-workarounds.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	28.02 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 io_event_irq.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 iommu.h	10.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipic.h	3.51 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	1.83 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq_work.h	252 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 irqflags.h	1.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 isa-bridge.h	654 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.62 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdebug.h	291 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kdump.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	4.02 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 keylargo.h	10.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kgdb.h	2.06 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kmap_types.h	434 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	3.75 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kup.h	1021 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_asm.h	5.46 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_book3s.h	12.06 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_book3s_32.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_book3s_64.h	12.62 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_book3s_asm.h	4.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_booke.h	2.68 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_booke_hv_asm.h	2.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_fpu.h	2.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_host.h	19.92 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 kvm_para.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_ppc.h	34.83 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 libata-portmap.h	249 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	501 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 livepatch.h	1.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 local.h	3.79 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lppaca.h	5.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 lv1call.h	18.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 machdep.h	9.7 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 macio.h	3.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mc146818rtc.h	943 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mce.h	5.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mediabay.h	1.34 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mm-arch-hooks.h	839 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mman.h	1.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu-40x.h	1.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu-44x.h	5.56 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu-8xx.h	8.6 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmu-book3e.h	9.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	9.2 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	6.26 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mmzone.h	1.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	2.47 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc5121.h	3.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc52xx.h	10.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc52xx_psc.h	9.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc5xxx.h	641 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc6xx.h	143 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc8260.h	742 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpc85xx.h	2.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpic.h	13.97 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 mpic_msgr.h	3.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 mpic_timer.h	1.39 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 msi_bitmap.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nmi.h	238 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📁 nohash	-	05/09/2024 07:14:16 AM	rwxr-xr-x
📄 nvram.h	3.21 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ohare.h	1.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 opal-api.h	29.34 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 opal.h	16.53 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 oprofile_impl.h	3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 paca.h	8.06 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 page.h	10.65 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 page_32.h	1.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page_64.h	2.93 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 parport.h	956 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pasemi_dma.h	23.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci-bridge.h	9.21 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pci.h	4.58 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 percpu.h	468 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 perf_event.h	1.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event_fsl_emb.h	1.42 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 perf_event_server.h	6.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	620 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-be-types.h	2.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable-types.h	1.94 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	2.45 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 plpar_wrappers.h	8.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmac_feature.h	13.08 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmac_low_i2c.h	3.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmac_pfunc.h	8.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmc.h	1.35 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pmi.h	1.77 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pnv-ocxl.h	1.4 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pnv-pci.h	3.22 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 powernv.h	1.57 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ppc-opcode.h	19.05 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ppc-pci.h	2.69 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppc4xx.h	530 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppc4xx_ocm.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ppc_asm.h	21.63 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 probes.h	2.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	15 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 prom.h	7.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ps3.h	15.44 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 ps3av.h	23.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ps3gpu.h	2.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ps3stor.h	1.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pte-common.h	6.27 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 pte-walk.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	7.14 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg.h	61.61 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 reg_8xx.h	4.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg_a2.h	6.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 reg_booke.h	36.17 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 reg_fsl_emb.h	3.65 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rheap.h	2.43 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 rio.h	637 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 rtas.h	14.67 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 runlatch.h	1.16 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scom.h	4.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	249 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	1.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 security_features.h	3.03 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 serial.h	677 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setjmp.h	630 bytes	06/16/2023 05:32:39 PM	rw-r--r--
📄 setup.h	2.44 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 sfp-machine.h	12.38 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 shmparam.h	206 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	225 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 slice.h	1.12 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 smp.h	6.13 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 smu.h	19.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	7.04 KB	06/16/2023 05:32:39 PM	rw-r--r--
📄 spinlock_types.h	424 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spu.h	25.28 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spu_csa.h	6.64 KB	01/28/2018 09:20:33 PM	rw-r--r--
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Editing: 8xx_immap.h

/*
 * MPC8xx Internal Memory Map
 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
 *
 * The I/O on the MPC860 is comprised of blocks of special registers
 * and the dual port ram for the Communication Processor Module.
 * Within this space are functional units such as the SIU, memory
 * controller, system timers, and other control functions.  It is
 * a combination that I found difficult to separate into logical
 * functional files.....but anyone else is welcome to try.  -- Dan
 */
#ifdef __KERNEL__
#ifndef __IMMAP_8XX__
#define __IMMAP_8XX__

/* System configuration registers.
*/
typedef	struct sys_conf {
	uint	sc_siumcr;
	uint	sc_sypcr;
	uint	sc_swt;
	char	res1[2];
	ushort	sc_swsr;
	uint	sc_sipend;
	uint	sc_simask;
	uint	sc_siel;
	uint	sc_sivec;
	uint	sc_tesr;
	char	res2[0xc];
	uint	sc_sdcr;
	char	res3[0x4c];
} sysconf8xx_t;

/* PCMCIA configuration registers.
*/
typedef struct pcmcia_conf {
	uint	pcmc_pbr0;
	uint	pcmc_por0;
	uint	pcmc_pbr1;
	uint	pcmc_por1;
	uint	pcmc_pbr2;
	uint	pcmc_por2;
	uint	pcmc_pbr3;
	uint	pcmc_por3;
	uint	pcmc_pbr4;
	uint	pcmc_por4;
	uint	pcmc_pbr5;
	uint	pcmc_por5;
	uint	pcmc_pbr6;
	uint	pcmc_por6;
	uint	pcmc_pbr7;
	uint	pcmc_por7;
	char	res1[0x20];
	uint	pcmc_pgcra;
	uint	pcmc_pgcrb;
	uint	pcmc_pscr;
	char	res2[4];
	uint	pcmc_pipr;
	char	res3[4];
	uint	pcmc_per;
	char	res4[4];
} pcmconf8xx_t;

/* Memory controller registers.
*/
typedef struct	mem_ctlr {
	uint	memc_br0;
	uint	memc_or0;
	uint	memc_br1;
	uint	memc_or1;
	uint	memc_br2;
	uint	memc_or2;
	uint	memc_br3;
	uint	memc_or3;
	uint	memc_br4;
	uint	memc_or4;
	uint	memc_br5;
	uint	memc_or5;
	uint	memc_br6;
	uint	memc_or6;
	uint	memc_br7;
	uint	memc_or7;
	char	res1[0x24];
	uint	memc_mar;
	uint	memc_mcr;
	char	res2[4];
	uint	memc_mamr;
	uint	memc_mbmr;
	ushort	memc_mstat;
	ushort	memc_mptpr;
	uint	memc_mdr;
	char	res3[0x80];
} memctl8xx_t;

/*-----------------------------------------------------------------------
 * BR - Memory Controller: Base Register					16-9
 */
#define BR_BA_MSK	0xffff8000	/* Base Address Mask			*/
#define BR_AT_MSK	0x00007000	/* Address Type Mask			*/
#define BR_PS_MSK	0x00000c00	/* Port Size Mask			*/
#define BR_PS_32	0x00000000	/* 32 bit port size			*/
#define BR_PS_16	0x00000800	/* 16 bit port size			*/
#define BR_PS_8		0x00000400	/*  8 bit port size			*/
#define BR_PARE		0x00000200	/* Parity Enable			*/
#define BR_WP		0x00000100	/* Write Protect			*/
#define BR_MS_MSK	0x000000c0	/* Machine Select Mask			*/
#define BR_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select		*/
#define BR_MS_UPMA	0x00000080	/* U.P.M.A Machine Select		*/
#define BR_MS_UPMB	0x000000c0	/* U.P.M.B Machine Select		*/
#define BR_V		0x00000001	/* Bank Valid				*/

/*-----------------------------------------------------------------------
 * OR - Memory Controller: Option Register				16-11
 */
#define OR_AM_MSK	0xffff8000	/* Address Mask Mask			*/
#define OR_ATM_MSK	0x00007000	/* Address Type Mask Mask		*/
#define OR_CSNT_SAM	0x00000800	/* Chip Select Negation Time/ Start	*/
					/* Address Multiplex			*/
#define OR_ACS_MSK	0x00000600	/* Address to Chip Select Setup mask	*/
#define OR_ACS_DIV1	0x00000000	/* CS is output at the same time	*/
#define OR_ACS_DIV4	0x00000400	/* CS is output 1/4 a clock later	*/
#define OR_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later	*/
#define OR_G5LA		0x00000400	/* Output #GPL5 on #GPL_A5		*/
#define OR_G5LS		0x00000200	/* Drive #GPL high on falling edge of...*/
#define OR_BI		0x00000100	/* Burst inhibit			*/
#define OR_SCY_MSK	0x000000f0	/* Cycle Length in Clocks		*/
#define OR_SCY_0_CLK	0x00000000	/* 0 clock cycles wait states		*/
#define OR_SCY_1_CLK	0x00000010	/* 1 clock cycles wait states		*/
#define OR_SCY_2_CLK	0x00000020	/* 2 clock cycles wait states		*/
#define OR_SCY_3_CLK	0x00000030	/* 3 clock cycles wait states		*/
#define OR_SCY_4_CLK	0x00000040	/* 4 clock cycles wait states		*/
#define OR_SCY_5_CLK	0x00000050	/* 5 clock cycles wait states		*/
#define OR_SCY_6_CLK	0x00000060	/* 6 clock cycles wait states		*/
#define OR_SCY_7_CLK	0x00000070	/* 7 clock cycles wait states		*/
#define OR_SCY_8_CLK	0x00000080	/* 8 clock cycles wait states		*/
#define OR_SCY_9_CLK	0x00000090	/* 9 clock cycles wait states		*/
#define OR_SCY_10_CLK	0x000000a0	/* 10 clock cycles wait states		*/
#define OR_SCY_11_CLK	0x000000b0	/* 11 clock cycles wait states		*/
#define OR_SCY_12_CLK	0x000000c0	/* 12 clock cycles wait states		*/
#define OR_SCY_13_CLK	0x000000d0	/* 13 clock cycles wait states		*/
#define OR_SCY_14_CLK	0x000000e0	/* 14 clock cycles wait states		*/
#define OR_SCY_15_CLK	0x000000f0	/* 15 clock cycles wait states		*/
#define OR_SETA		0x00000008	/* External Transfer Acknowledge	*/
#define OR_TRLX		0x00000004	/* Timing Relaxed			*/
#define OR_EHTR		0x00000002	/* Extended Hold Time on Read		*/

/* System Integration Timers.
*/
typedef struct	sys_int_timers {
	ushort	sit_tbscr;
	char	res0[0x02];
	uint	sit_tbreff0;
	uint	sit_tbreff1;
	char	res1[0x14];
	ushort	sit_rtcsc;
	char	res2[0x02];
	uint	sit_rtc;
	uint	sit_rtsec;
	uint	sit_rtcal;
	char	res3[0x10];
	ushort	sit_piscr;
	char	res4[2];
	uint	sit_pitc;
	uint	sit_pitr;
	char	res5[0x34];
} sit8xx_t;

#define TBSCR_TBIRQ_MASK	((ushort)0xff00)
#define TBSCR_REFA		((ushort)0x0080)
#define TBSCR_REFB		((ushort)0x0040)
#define TBSCR_REFAE		((ushort)0x0008)
#define TBSCR_REFBE		((ushort)0x0004)
#define TBSCR_TBF		((ushort)0x0002)
#define TBSCR_TBE		((ushort)0x0001)

#define RTCSC_RTCIRQ_MASK	((ushort)0xff00)
#define RTCSC_SEC		((ushort)0x0080)
#define RTCSC_ALR		((ushort)0x0040)
#define RTCSC_38K		((ushort)0x0010)
#define RTCSC_SIE		((ushort)0x0008)
#define RTCSC_ALE		((ushort)0x0004)
#define RTCSC_RTF		((ushort)0x0002)
#define RTCSC_RTE		((ushort)0x0001)

#define PISCR_PIRQ_MASK		((ushort)0xff00)
#define PISCR_PS		((ushort)0x0080)
#define PISCR_PIE		((ushort)0x0004)
#define PISCR_PTF		((ushort)0x0002)
#define PISCR_PTE		((ushort)0x0001)

/* Clocks and Reset.
*/
typedef struct clk_and_reset {
	uint	car_sccr;
	uint	car_plprcr;
	uint	car_rsr;
	char	res[0x74];        /* Reserved area                  */
} car8xx_t;

/* System Integration Timers keys.
*/
typedef struct sitk {
	uint	sitk_tbscrk;
	uint	sitk_tbreff0k;
	uint	sitk_tbreff1k;
	uint	sitk_tbk;
	char	res1[0x10];
	uint	sitk_rtcsck;
	uint	sitk_rtck;
	uint	sitk_rtseck;
	uint	sitk_rtcalk;
	char	res2[0x10];
	uint	sitk_piscrk;
	uint	sitk_pitck;
	char	res3[0x38];
} sitk8xx_t;

/* Clocks and reset keys.
*/
typedef struct cark {
	uint	cark_sccrk;
	uint	cark_plprcrk;
	uint	cark_rsrk;
	char	res[0x474];
} cark8xx_t;

/* The key to unlock registers maintained by keep-alive power.
*/
#define KAPWR_KEY	((unsigned int)0x55ccaa33)

/* Video interface.  MPC823 Only.
*/
typedef struct vid823 {
	ushort	vid_vccr;
	ushort	res1;
	u_char	vid_vsr;
	u_char	res2;
	u_char	vid_vcmr;
	u_char	res3;
	uint	vid_vbcb;
	uint	res4;
	uint	vid_vfcr0;
	uint	vid_vfaa0;
	uint	vid_vfba0;
	uint	vid_vfcr1;
	uint	vid_vfaa1;
	uint	vid_vfba1;
	u_char	res5[0x18];
} vid823_t;

/* LCD interface.  823 Only.
*/
typedef struct lcd {
	uint	lcd_lccr;
	uint	lcd_lchcr;
	uint	lcd_lcvcr;
	char	res1[4];
	uint	lcd_lcfaa;
	uint	lcd_lcfba;
	char	lcd_lcsr;
	char	res2[0x7];
} lcd823_t;

/* I2C
*/
typedef struct i2c {
	u_char	i2c_i2mod;
	char	res1[3];
	u_char	i2c_i2add;
	char	res2[3];
	u_char	i2c_i2brg;
	char	res3[3];
	u_char	i2c_i2com;
	char	res4[3];
	u_char	i2c_i2cer;
	char	res5[3];
	u_char	i2c_i2cmr;
	char	res6[0x8b];
} i2c8xx_t;

/* DMA control/status registers.
*/
typedef struct sdma_csr {
	char	res1[4];
	uint	sdma_sdar;
	u_char	sdma_sdsr;
	char	res3[3];
	u_char	sdma_sdmr;
	char	res4[3];
	u_char	sdma_idsr1;
	char	res5[3];
	u_char	sdma_idmr1;
	char	res6[3];
	u_char	sdma_idsr2;
	char	res7[3];
	u_char	sdma_idmr2;
	char	res8[0x13];
} sdma8xx_t;

/* Communication Processor Module Interrupt Controller.
*/
typedef struct cpm_ic {
	ushort	cpic_civr;
	char	res[0xe];
	uint	cpic_cicr;
	uint	cpic_cipr;
	uint	cpic_cimr;
	uint	cpic_cisr;
} cpic8xx_t;

/* Input/Output Port control/status registers.
*/
typedef struct io_port {
	ushort	iop_padir;
	ushort	iop_papar;
	ushort	iop_paodr;
	ushort	iop_padat;
	char	res1[8];
	ushort	iop_pcdir;
	ushort	iop_pcpar;
	ushort	iop_pcso;
	ushort	iop_pcdat;
	ushort	iop_pcint;
	char	res2[6];
	ushort	iop_pddir;
	ushort	iop_pdpar;
	char	res3[2];
	ushort	iop_pddat;
	uint	utmode;
	char	res4[4];
} iop8xx_t;

/* Communication Processor Module Timers
*/
typedef struct cpm_timers {
	ushort	cpmt_tgcr;
	char	res1[0xe];
	ushort	cpmt_tmr1;
	ushort	cpmt_tmr2;
	ushort	cpmt_trr1;
	ushort	cpmt_trr2;
	ushort	cpmt_tcr1;
	ushort	cpmt_tcr2;
	ushort	cpmt_tcn1;
	ushort	cpmt_tcn2;
	ushort	cpmt_tmr3;
	ushort	cpmt_tmr4;
	ushort	cpmt_trr3;
	ushort	cpmt_trr4;
	ushort	cpmt_tcr3;
	ushort	cpmt_tcr4;
	ushort	cpmt_tcn3;
	ushort	cpmt_tcn4;
	ushort	cpmt_ter1;
	ushort	cpmt_ter2;
	ushort	cpmt_ter3;
	ushort	cpmt_ter4;
	char	res2[8];
} cpmtimer8xx_t;

/* Finally, the Communication Processor stuff.....
*/
typedef struct scc {		/* Serial communication channels */
	uint	scc_gsmrl;
	uint	scc_gsmrh;
	ushort	scc_psmr;
	char	res1[2];
	ushort	scc_todr;
	ushort	scc_dsr;
	ushort	scc_scce;
	char	res2[2];
	ushort	scc_sccm;
	char	res3;
	u_char	scc_sccs;
	char	res4[8];
} scc_t;

typedef struct smc {		/* Serial management channels */
	char	res1[2];
	ushort	smc_smcmr;
	char	res2[2];
	u_char	smc_smce;
	char	res3[3];
	u_char	smc_smcm;
	char	res4[5];
} smc_t;

/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
 * it fits within the address space.
 */

typedef struct fec {
	uint	fec_addr_low;		/* lower 32 bits of station address	*/
	ushort	fec_addr_high;		/* upper 16 bits of station address	*/
	ushort	res1;			/* reserved				*/
	uint	fec_grp_hash_table_high;	/* upper 32-bits of hash table		*/
	uint	fec_grp_hash_table_low;	/* lower 32-bits of hash table		*/
	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
	uint	fec_r_buff_size;	/* Rx buffer size			*/
	uint	res2[9];		/* reserved				*/
	uint	fec_ecntrl;		/* ethernet control register		*/
	uint	fec_ievent;		/* interrupt event register		*/
	uint	fec_imask;		/* interrupt mask register		*/
	uint	fec_ivec;		/* interrupt level and vector status	*/
	uint	fec_r_des_active;	/* Rx ring updated flag			*/
	uint	fec_x_des_active;	/* Tx ring updated flag			*/
	uint	res3[10];		/* reserved				*/
	uint	fec_mii_data;		/* MII data register			*/
	uint	fec_mii_speed;		/* MII speed control register		*/
	uint	res4[17];		/* reserved				*/
	uint	fec_r_bound;		/* end of RAM (read-only)		*/
	uint	fec_r_fstart;		/* Rx FIFO start address		*/
	uint	res5[6];		/* reserved				*/
	uint	fec_x_fstart;		/* Tx FIFO start address		*/
	uint	res6[17];		/* reserved				*/
	uint	fec_fun_code;		/* fec SDMA function code		*/
	uint	res7[3];		/* reserved				*/
	uint	fec_r_cntrl;		/* Rx control register			*/
	uint	fec_r_hash;		/* Rx hash register			*/
	uint	res8[14];		/* reserved				*/
	uint	fec_x_cntrl;		/* Tx control register			*/
	uint	res9[0x1e];		/* reserved				*/
} fec_t;

/* The FEC and LCD color map share the same address space....
 * I guess we will never see an 823T :-).
 */
union fec_lcd {
	fec_t	fl_un_fec;
	u_char	fl_un_cmap[0x200];
};

typedef struct comm_proc {
	/* General control and status registers.
	*/
	ushort	cp_cpcr;
	u_char	res1[2];
	ushort	cp_rccr;
	u_char	res2;
	u_char	cp_rmds;
	u_char	res3[4];
	ushort	cp_cpmcr1;
	ushort	cp_cpmcr2;
	ushort	cp_cpmcr3;
	ushort	cp_cpmcr4;
	u_char	res4[2];
	ushort	cp_rter;
	u_char	res5[2];
	ushort	cp_rtmr;
	u_char	res6[0x14];

/* Baud rate generators.
	*/
	uint	cp_brgc1;
	uint	cp_brgc2;
	uint	cp_brgc3;
	uint	cp_brgc4;

/* Serial Communication Channels.
	*/
	scc_t	cp_scc[4];

/* Serial Management Channels.
	*/
	smc_t	cp_smc[2];

/* Serial Peripheral Interface.
	*/
	ushort	cp_spmode;
	u_char	res7[4];
	u_char	cp_spie;
	u_char	res8[3];
	u_char	cp_spim;
	u_char	res9[2];
	u_char	cp_spcom;
	u_char	res10[2];

/* Parallel Interface Port.
	*/
	u_char	res11[2];
	ushort	cp_pipc;
	u_char	res12[2];
	ushort	cp_ptpr;
	uint	cp_pbdir;
	uint	cp_pbpar;
	u_char	res13[2];
	ushort	cp_pbodr;
	uint	cp_pbdat;

/* Port E - MPC87x/88x only.
	 */
	uint	cp_pedir;
	uint	cp_pepar;
	uint	cp_peso;
	uint	cp_peodr;
	uint	cp_pedat;

/* Communications Processor Timing Register -
	   Contains RMII Timing for the FECs on MPC87x/88x only.
	*/
	uint	cp_cptr;

/* Serial Interface and Time Slot Assignment.
	*/
	uint	cp_simode;
	u_char	cp_sigmr;
	u_char	res15;
	u_char	cp_sistr;
	u_char	cp_sicmr;
	u_char	res16[4];
	uint	cp_sicr;
	uint	cp_sirp;
	u_char	res17[0xc];

/* 256 bytes of MPC823 video controller RAM array.
	*/
	u_char	cp_vcram[0x100];
	u_char	cp_siram[0x200];

/* The fast ethernet controller is not really part of the CPM,
	 * but it resides in the address space.
	 * The LCD color map is also here.
	 */
	union	fec_lcd	fl_un;
#define cp_fec		fl_un.fl_un_fec
#define lcd_cmap	fl_un.fl_un_cmap
	char	res18[0xE00];

/* The DUET family has a second FEC here */
	fec_t	cp_fec2;
#define cp_fec1	cp_fec	/* consistency macro */

/* Dual Ported RAM follows.
	 * There are many different formats for this memory area
	 * depending upon the devices used and options chosen.
	 * Some processors don't have all of it populated.
	 */
	u_char	cp_dpmem[0x1C00];	/* BD / Data / ucode */
	u_char	cp_dparam[0x400];	/* Parameter RAM */
} cpm8xx_t;

/* Internal memory map.
*/
typedef struct immap {
	sysconf8xx_t	im_siu_conf;	/* SIU Configuration */
	pcmconf8xx_t	im_pcmcia;	/* PCMCIA Configuration */
	memctl8xx_t	im_memctl;	/* Memory Controller */
	sit8xx_t	im_sit;		/* System integration timers */
	car8xx_t	im_clkrst;	/* Clocks and reset */
	sitk8xx_t	im_sitk;	/* Sys int timer keys */
	cark8xx_t	im_clkrstk;	/* Clocks and reset keys */
	vid823_t	im_vid;		/* Video (823 only) */
	lcd823_t	im_lcd;		/* LCD (823 only) */
	i2c8xx_t	im_i2c;		/* I2C control/status */
	sdma8xx_t	im_sdma;	/* SDMA control/status */
	cpic8xx_t	im_cpic;	/* CPM Interrupt Controller */
	iop8xx_t	im_ioport;	/* IO Port control/status */
	cpmtimer8xx_t	im_cpmtimer;	/* CPM timers */
	cpm8xx_t	im_cpm;		/* Communication processor */
} immap_t;

#endif /* __IMMAP_8XX__ */
#endif /* __KERNEL__ */