OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	557 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 airq.h	3.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 alternative-asm.h	3.07 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 alternative.h	4.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ap.h	9.9 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 appldata.h	1.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 archrandom.h	1.1 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 asm-prototypes.h	227 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	5.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic_ops.h	4.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	1.84 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 bitops.h	10.13 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bug.h	1.49 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 bugs.h	441 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	387 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ccwdev.h	7.99 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ccwgroup.h	2.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 checksum.h	3.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 chpid.h	974 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cio.h	8.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 clp.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmb.h	425 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	1.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 compat.h	7.9 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpacf.h	16.8 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpcmd.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu.h	549 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpu_mf.h	8.99 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 cpufeature.h	963 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cputime.h	805 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 crw.h	1.86 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 css_chars.h	769 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 ctl_reg.h	2.89 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 current.h	405 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 debug.h	8.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	721 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 diag.h	5.94 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 dis.h	637 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	621 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma.h	456 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 eadm.h	2.03 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ebcdic.h	1.41 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	10.36 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 exec.h	269 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extable.h	875 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 extmem.h	804 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 facility.h	2.44 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 fcx.h	7.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📁 fpu	-	11/17/2022 06:42:21 AM	rwxr-xr-x
📄 ftrace.h	1.66 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 futex.h	2.07 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 gmap.h	4.93 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hardirq.h	670 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 hugetlb.h	2.82 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 hw_irq.h	249 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 idals.h	5.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 idle.h	709 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	2.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ipl.h	3.6 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	2.55 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	1.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 isc.h	1000 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 itcw.h	950 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 jump_label.h	1.36 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kdebug.h	386 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 kexec.h	1.32 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kprobes.h	2.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 kvm_host.h	22.24 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 kvm_para.h	5.78 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	633 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 livepatch.h	461 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 lowcore.h	6.29 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmu.h	1.19 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmu_context.h	3.84 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 mmzone.h	316 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 module.h	802 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 nmi.h	3.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 nospec-branch.h	342 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 nospec-insn.h	3.81 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 numa.h	730 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 os_info.h	1.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page-states.h	486 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	5.12 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci.h	6.26 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pci_clp.h	4.25 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_debug.h	608 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_dma.h	5.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_insn.h	2.59 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pci_io.h	4.58 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 percpu.h	6.43 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 perf_event.h	2.71 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	4.32 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pgtable.h	47.7 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 pkey.h	4.23 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 preempt.h	3.25 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 processor.h	10.42 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 ptrace.h	5.27 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 qdio.h	11.67 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 reset.h	471 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 runtime_instr.h	1.76 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 schid.h	525 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sclp.h	3.38 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 scsw.h	24.1 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 seccomp.h	516 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sections.h	155 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 segment.h	93 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	147 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 set_memory.h	779 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 setup.h	4.44 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 shmparam.h	285 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 signal.h	644 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 sigp.h	1.8 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	2.45 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 sparsemem.h	214 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	3.53 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	437 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 stp.h	1.26 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	4.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 switch_to.h	1.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	2.63 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 sysinfo.h	4.22 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 termios.h	685 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	3.15 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 timex.h	6.15 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlb.h	5.71 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlbflush.h	3.52 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 topology.h	2.69 KB	11/01/2022 04:52:05 PM	rw-r--r--
📁 trace	-	11/17/2022 06:42:21 AM	rwxr-xr-x
📄 uaccess.h	6.57 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 unistd.h	1.03 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uprobes.h	588 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 user.h	3.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 vdso.h	1.8 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 vga.h	170 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vtime.h	182 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vtimer.h	866 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 vx-insn.h	10.66 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 xor.h	454 bytes	01/28/2018 09:20:33 PM	rw-r--r--

Editing: ap.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Adjunct processor (AP) interfaces
 *
 * Copyright IBM Corp. 2017
 *
 * Author(s): Tony Krowiak <akrowia@linux.vnet.ibm.com>
 *	      Martin Schwidefsky <schwidefsky@de.ibm.com>
 *	      Harald Freudenberger <freude@de.ibm.com>
 */

#ifndef _ASM_S390_AP_H_
#define _ASM_S390_AP_H_

/**
 * The ap_qid_t identifier of an ap queue.
 * If the AP facilities test (APFT) facility is available,
 * card and queue index are 8 bit values, otherwise
 * card index is 6 bit and queue index a 4 bit value.
 */
typedef unsigned int ap_qid_t;

#define AP_MKQID(_card, _queue) (((_card) & 0xff) << 8 | ((_queue) & 0xff))
#define AP_QID_CARD(_qid) (((_qid) >> 8) & 0xff)
#define AP_QID_QUEUE(_qid) ((_qid) & 0xff)

/**
 * struct ap_queue_status - Holds the AP queue status.
 * @queue_empty: Shows if queue is empty
 * @replies_waiting: Waiting replies
 * @queue_full: Is 1 if the queue is full
 * @irq_enabled: Shows if interrupts are enabled for the AP
 * @response_code: Holds the 8 bit response code
 *
 * The ap queue status word is returned by all three AP functions
 * (PQAP, NQAP and DQAP).  There's a set of flags in the first
 * byte, followed by a 1 byte response code.
 */
struct ap_queue_status {
	unsigned int queue_empty	: 1;
	unsigned int replies_waiting	: 1;
	unsigned int queue_full		: 1;
	unsigned int _pad1		: 4;
	unsigned int irq_enabled	: 1;
	unsigned int response_code	: 8;
	unsigned int _pad2		: 16;
};

/**
 * ap_intructions_available() - Test if AP instructions are available.
 *
 * Returns 1 if the AP instructions are installed, otherwise 0.
 */
static inline int ap_instructions_available(void)
{
	register unsigned long reg0 asm ("0") = AP_MKQID(0, 0);
	register unsigned long reg1 asm ("1") = 0;
	register unsigned long reg2 asm ("2") = 0;

asm volatile(
		"   .long 0xb2af0000\n"		/* PQAP(TAPQ) */
		"0: la    %0,1\n"
		"1:\n"
		EX_TABLE(0b, 1b)
		: "+d" (reg1), "+d" (reg2)
		: "d" (reg0)
		: "cc");
	return reg1;
}

/**
 * ap_tapq(): Test adjunct processor queue.
 * @qid: The AP queue number
 * @info: Pointer to queue descriptor
 *
 * Returns AP queue status structure.
 */
static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
{
	register unsigned long reg0 asm ("0") = qid;
	register struct ap_queue_status reg1 asm ("1");
	register unsigned long reg2 asm ("2");

asm volatile(".long 0xb2af0000"		/* PQAP(TAPQ) */
		     : "=d" (reg1), "=d" (reg2)
		     : "d" (reg0)
		     : "cc");
	if (info)
		*info = reg2;
	return reg1;
}

/**
 * ap_test_queue(): Test adjunct processor queue.
 * @qid: The AP queue number
 * @tbit: Test facilities bit
 * @info: Pointer to queue descriptor
 *
 * Returns AP queue status structure.
 */
static inline struct ap_queue_status ap_test_queue(ap_qid_t qid,
						   int tbit,
						   unsigned long *info)
{
	if (tbit)
		qid |= 1UL << 23; /* set T bit*/
	return ap_tapq(qid, info);
}

/**
 * ap_pqap_rapq(): Reset adjunct processor queue.
 * @qid: The AP queue number
 *
 * Returns AP queue status structure.
 */
static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
{
	register unsigned long reg0 asm ("0") = qid | (1UL << 24);
	register struct ap_queue_status reg1 asm ("1");

asm volatile(
		".long 0xb2af0000"		/* PQAP(RAPQ) */
		: "=d" (reg1)
		: "d" (reg0)
		: "cc");
	return reg1;
}

/**
 * ap_pqap_zapq(): Reset and zeroize adjunct processor queue.
 * @qid: The AP queue number
 *
 * Returns AP queue status structure.
 */
static inline struct ap_queue_status ap_zapq(ap_qid_t qid)
{
	register unsigned long reg0 asm ("0") = qid | (2UL << 24);
	register struct ap_queue_status reg1 asm ("1");

asm volatile(
		".long 0xb2af0000"		/* PQAP(ZAPQ) */
		: "=d" (reg1)
		: "d" (reg0)
		: "cc");
	return reg1;
}

/**
 * struct ap_config_info - convenience struct for AP crypto
 * config info as returned by the ap_qci() function.
 */
struct ap_config_info {
	unsigned int apsc	 : 1;	/* S bit */
	unsigned int apxa	 : 1;	/* N bit */
	unsigned int qact	 : 1;	/* C bit */
	unsigned int rc8a	 : 1;	/* R bit */
	unsigned char _reserved1 : 4;
	unsigned char _reserved2[3];
	unsigned char Na;		/* max # of APs - 1 */
	unsigned char Nd;		/* max # of Domains - 1 */
	unsigned char _reserved3[10];
	unsigned int apm[8];		/* AP ID mask */
	unsigned int aqm[8];		/* AP (usage) queue mask */
	unsigned int adm[8];		/* AP (control) domain mask */
	unsigned char _reserved4[16];
} __aligned(8);

/**
 * ap_qci(): Get AP configuration data
 *
 * Returns 0 on success, or -EOPNOTSUPP.
 */
static inline int ap_qci(struct ap_config_info *config)
{
	register unsigned long reg0 asm ("0") = 4UL << 24;
	register unsigned long reg1 asm ("1") = -EOPNOTSUPP;
	register struct ap_config_info *reg2 asm ("2") = config;

asm volatile(
		".long 0xb2af0000\n"		/* PQAP(QCI) */
		"0: la    %0,0\n"
		"1:\n"
		EX_TABLE(0b, 1b)
		: "+d" (reg1)
		: "d" (reg0), "d" (reg2)
		: "cc", "memory");

return reg1;
}

/*
 * struct ap_qirq_ctrl - convenient struct for easy invocation
 * of the ap_aqic() function. This struct is passed as GR1
 * parameter to the PQAP(AQIC) instruction. For details please
 * see the AR documentation.
 */
struct ap_qirq_ctrl {
	unsigned int _res1 : 8;
	unsigned int zone  : 8;	/* zone info */
	unsigned int ir    : 1;	/* ir flag: enable (1) or disable (0) irq */
	unsigned int _res2 : 4;
	unsigned int gisc  : 3;	/* guest isc field */
	unsigned int _res3 : 6;
	unsigned int gf    : 2;	/* gisa format */
	unsigned int _res4 : 1;
	unsigned int gisa  : 27;	/* gisa origin */
	unsigned int _res5 : 1;
	unsigned int isc   : 3;	/* irq sub class */
};

/**
 * ap_aqic(): Control interruption for a specific AP.
 * @qid: The AP queue number
 * @qirqctrl: struct ap_qirq_ctrl (64 bit value)
 * @ind: The notification indicator byte
 *
 * Returns AP queue status.
 */
static inline struct ap_queue_status ap_aqic(ap_qid_t qid,
					     struct ap_qirq_ctrl qirqctrl,
					     void *ind)
{
	register unsigned long reg0 asm ("0") = qid | (3UL << 24);
	register union {
		unsigned long value;
		struct ap_qirq_ctrl qirqctrl;
		struct ap_queue_status status;
	} reg1 asm ("1");
	register void *reg2 asm ("2") = ind;

reg1.qirqctrl = qirqctrl;

asm volatile(
		".long 0xb2af0000"		/* PQAP(AQIC) */
		: "+d" (reg1)
		: "d" (reg0), "d" (reg2)
		: "cc");

return reg1.status;
}

/*
 * union ap_qact_ap_info - used together with the
 * ap_aqic() function to provide a convenient way
 * to handle the ap info needed by the qact function.
 */
union ap_qact_ap_info {
	unsigned long val;
	struct {
		unsigned int	  : 3;
		unsigned int mode : 3;
		unsigned int	  : 26;
		unsigned int cat  : 8;
		unsigned int	  : 8;
		unsigned char ver[2];
	};
};

/**
 * ap_qact(): Query AP combatibility type.
 * @qid: The AP queue number
 * @apinfo: On input the info about the AP queue. On output the
 *	    alternate AP queue info provided by the qact function
 *	    in GR2 is stored in.
 *
 * Returns AP queue status. Check response_code field for failures.
 */
static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit,
					     union ap_qact_ap_info *apinfo)
{
	register unsigned long reg0 asm ("0") = qid | (5UL << 24)
		| ((ifbit & 0x01) << 22);
	register union {
		unsigned long value;
		struct ap_queue_status status;
	} reg1 asm ("1");
	register unsigned long reg2 asm ("2");

reg1.value = apinfo->val;

asm volatile(
		".long 0xb2af0000"		/* PQAP(QACT) */
		: "+d" (reg1), "=d" (reg2)
		: "d" (reg0)
		: "cc");
	apinfo->val = reg2;
	return reg1.status;
}

/**
 * ap_nqap(): Send message to adjunct processor queue.
 * @qid: The AP queue number
 * @psmid: The program supplied message identifier
 * @msg: The message text
 * @length: The message length
 *
 * Returns AP queue status structure.
 * Condition code 1 on NQAP can't happen because the L bit is 1.
 * Condition code 2 on NQAP also means the send is incomplete,
 * because a segment boundary was reached. The NQAP is repeated.
 */
static inline struct ap_queue_status ap_nqap(ap_qid_t qid,
					     unsigned long long psmid,
					     void *msg, size_t length)
{
	register unsigned long reg0 asm ("0") = qid | 0x40000000UL;
	register struct ap_queue_status reg1 asm ("1");
	register unsigned long reg2 asm ("2") = (unsigned long) msg;
	register unsigned long reg3 asm ("3") = (unsigned long) length;
	register unsigned long reg4 asm ("4") = (unsigned int) (psmid >> 32);
	register unsigned long reg5 asm ("5") = psmid & 0xffffffff;

asm volatile (
		"0: .long 0xb2ad0042\n"		/* NQAP */
		"   brc   2,0b"
		: "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3)
		: "d" (reg4), "d" (reg5)
		: "cc", "memory");
	return reg1;
}

/**
 * ap_dqap(): Receive message from adjunct processor queue.
 * @qid: The AP queue number
 * @psmid: Pointer to program supplied message identifier
 * @msg: The message text
 * @length: The message length
 *
 * Returns AP queue status structure.
 * Condition code 1 on DQAP means the receive has taken place
 * but only partially.	The response is incomplete, hence the
 * DQAP is repeated.
 * Condition code 2 on DQAP also means the receive is incomplete,
 * this time because a segment boundary was reached. Again, the
 * DQAP is repeated.
 * Note that gpr2 is used by the DQAP instruction to keep track of
 * any 'residual' length, in case the instruction gets interrupted.
 * Hence it gets zeroed before the instruction.
 */
static inline struct ap_queue_status ap_dqap(ap_qid_t qid,
					     unsigned long long *psmid,
					     void *msg, size_t length)
{
	register unsigned long reg0 asm("0") = qid | 0x80000000UL;
	register struct ap_queue_status reg1 asm ("1");
	register unsigned long reg2 asm("2") = 0UL;
	register unsigned long reg4 asm("4") = (unsigned long) msg;
	register unsigned long reg5 asm("5") = (unsigned long) length;
	register unsigned long reg6 asm("6") = 0UL;
	register unsigned long reg7 asm("7") = 0UL;

asm volatile(
		"0: .long 0xb2ae0064\n"		/* DQAP */
		"   brc   6,0b\n"
		: "+d" (reg0), "=d" (reg1), "+d" (reg2),
		  "+d" (reg4), "+d" (reg5), "+d" (reg6), "+d" (reg7)
		: : "cc", "memory");
	*psmid = (((unsigned long long) reg6) << 32) + reg7;
	return reg1;
}

#endif /* _ASM_S390_AP_H_ */