OXIESEC PANEL

Name	Size	Modified	Perms
📁 ..	-	11/17/2022 06:42:16 AM	rwxr-xr-x
📄 Kbuild	997 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 asm-offsets.h	35 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 atomic.h	3.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 barrier.h	203 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📁 bitops	-	11/17/2022 06:42:21 AM	rwxr-xr-x
📄 bitops.h	1.5 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cache.h	888 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 cacheflush.h	3.37 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cmpxchg.h	3.92 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 cpuinfo.h	970 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 delay.h	670 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 dma-mapping.h	968 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 elf.h	2.02 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 fixmap.h	2.74 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 futex.h	2.24 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 io.h	1.31 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 irq.h	835 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 irqflags.h	866 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 linkage.h	764 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu.h	728 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 mmu_context.h	1.3 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 page.h	2.54 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgalloc.h	2.57 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 pgtable.h	13.96 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 processor.h	2.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 ptrace.h	3.33 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 serial.h	1.11 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 smp.h	822 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock.h	985 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spinlock_types.h	188 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 spr.h	1.17 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 spr_defs.h	22.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 string.h	324 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscall.h	1.91 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 syscalls.h	1.04 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 thread_info.h	3.85 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 time.h	627 bytes	01/28/2018 09:20:33 PM	rw-r--r--
📄 timex.h	914 bytes	11/01/2022 04:52:05 PM	rw-r--r--
📄 tlb.h	1.01 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 tlbflush.h	2.05 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 uaccess.h	7.98 KB	11/01/2022 04:52:05 PM	rw-r--r--
📄 unaligned.h	1.7 KB	01/28/2018 09:20:33 PM	rw-r--r--
📄 unwinder.h	557 bytes	01/28/2018 09:20:33 PM	rw-r--r--

Editing: cacheflush.h

/*
 * OpenRISC Linux
 *
 * Linux architectural port borrowing liberally from similar works of
 * others.  All original copyrights apply as per the original source
 * declaration.
 *
 * OpenRISC implementation:
 * Copyright (C) Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de>
 * et al.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __ASM_CACHEFLUSH_H
#define __ASM_CACHEFLUSH_H

#include <linux/mm.h>

/*
 * Helper function for flushing or invalidating entire pages from data
 * and instruction caches. SMP needs a little extra work, since we need
 * to flush the pages on all cpus.
 */
extern void local_dcache_page_flush(struct page *page);
extern void local_icache_page_inv(struct page *page);

/*
 * Data cache flushing always happen on the local cpu. Instruction cache
 * invalidations need to be broadcasted to all other cpu in the system in
 * case of SMP configurations.
 */
#ifndef CONFIG_SMP
#define dcache_page_flush(page)      local_dcache_page_flush(page)
#define icache_page_inv(page)        local_icache_page_inv(page)
#else  /* CONFIG_SMP */
#define dcache_page_flush(page)      local_dcache_page_flush(page)
#define icache_page_inv(page)        smp_icache_page_inv(page)
extern void smp_icache_page_inv(struct page *page);
#endif /* CONFIG_SMP */

/*
 * Synchronizes caches. Whenever a cpu writes executable code to memory, this
 * should be called to make sure the processor sees the newly written code.
 */
static inline void sync_icache_dcache(struct page *page)
{
	if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
		dcache_page_flush(page);
	icache_page_inv(page);
}

/*
 * Pages with this bit set need not be flushed/invalidated, since
 * they have not changed since last flush. New pages start with
 * PG_arch_1 not set and are therefore dirty by default.
 */
#define PG_dc_clean                  PG_arch_1

#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
static inline void flush_dcache_page(struct page *page)
{
	clear_bit(PG_dc_clean, &page->flags);
}

/*
 * Other interfaces are not required since we do not have virtually
 * indexed or tagged caches. So we can use the default here.
 */
#define flush_cache_all()				do { } while (0)
#define flush_cache_mm(mm)				do { } while (0)
#define flush_cache_dup_mm(mm)				do { } while (0)
#define flush_cache_range(vma, start, end)		do { } while (0)
#define flush_cache_page(vma, vmaddr, pfn)		do { } while (0)
#define flush_dcache_mmap_lock(mapping)			do { } while (0)
#define flush_dcache_mmap_unlock(mapping)		do { } while (0)
#define flush_icache_range(start, end)			do { } while (0)
#define flush_icache_page(vma, pg)			do { } while (0)
#define flush_icache_user_range(vma, pg, adr, len)	do { } while (0)
#define flush_cache_vmap(start, end)			do { } while (0)
#define flush_cache_vunmap(start, end)			do { } while (0)

#define copy_to_user_page(vma, page, vaddr, dst, src, len)           \
	do {                                                         \
		memcpy(dst, src, len);                               \
		if (vma->vm_flags & VM_EXEC)                         \
			sync_icache_dcache(page);                    \
	} while (0)

#define copy_from_user_page(vma, page, vaddr, dst, src, len)         \
	memcpy(dst, src, len)

#endif /* __ASM_CACHEFLUSH_H */